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S3_<op1>_<Cn>_<Cm>_<op2>, IMPLEMENTATION DEFINED registers

The S3_<op1>_<Cn>_<Cm>_<op2> characteristics are:

Purpose

This area of the instruction set space is reserved for IMPLEMENTATION DEFINED registers.

Configuration

Attributes

S3_<op1>_<Cn>_<Cm>_<op2> is a 64-bit register.

Field descriptions

The S3_<op1>_<Cn>_<Cm>_<op2> bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED
313029282726252423222120191817161514131211109876543210

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

Accessing the S3_<op1>_<Cn>_<Cm>_<op2>

Accesses to this register use the following encodings:

MRS <Xt>, S3_<op1>_C<Cn>_C<Cm>_<op2>

op0CRnop1op2CRm
0b110b1x110b[op1:2:0]0b[op2:2:0]0b[Cm:3:0]
if PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.TIDCP == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        IMPLEMENTATION_DEFINED "";
else
    IMPLEMENTATION_DEFINED "";
              

MSR S3_<op1>_C<Cn>_C<Cm>_<op2>, <Xt>

op0CRnop1op2CRm
0b110b1x110b[op1:2:0]0b[op2:2:0]0b[Cm:3:0]
if PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.TIDCP == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        IMPLEMENTATION_DEFINED "";
else
    IMPLEMENTATION_DEFINED "";
              


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