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TCO, Tag Check Override

The TCO characteristics are:

Purpose

When ARMv8.5-MemTag is implemented, this register allows tag checks to be disabled globally.

Configuration

This register is present only when ARMv8.5-MemTag is implemented. Otherwise, direct accesses to TCO are UNDEFINED.

Attributes

TCO is a 64-bit register.

Field descriptions

The TCO bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
000000TCO0000000000000000000000000
313029282726252423222120191817161514131211109876543210

Bits [63:26]

Reserved, RES0.

TCO, bit [25]

From Armv8.5:

Allows memory tag checks to be globally disabled.

TCOMeaning
0b0

Loads and Stores are not affected by this control.

0b1

Loads and Stores are unchecked.


Otherwise:

Reserved, RES0.

Bits [24:0]

Reserved, RES0.

Accessing the TCO

For details on the operation of the MSR (immediate) accessor, see MSR (immediate).

Accesses to this register use the following encodings:

MRS <Xt>, TCO

CRnop0op1op2CRm
0b01000b110b0110b1110b0010
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    return Zeros(38):PSTATE.TCO:Zeros(25);
elsif PSTATE.EL == EL2 then
    return Zeros(38):PSTATE.TCO:Zeros(25);
elsif PSTATE.EL == EL3 then
    return Zeros(38):PSTATE.TCO:Zeros(25);
              

MSR TCO, <Xt>

CRnop0op1op2CRm
0b01000b110b0110b1110b0010
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    PSTATE.TCO = X[t]<25>;
elsif PSTATE.EL == EL2 then
    PSTATE.TCO = X[t]<25>;
elsif PSTATE.EL == EL3 then
    PSTATE.TCO = X[t]<25>;
              

MSR TCO, #<imm>

CRnop0op1op2
0b01000b000b0110b100


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