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External register index by offset
Below are indexes for external registers in the following blocks:
- AMU
- CTI
- Debug
- GIC CPU interface
- GIC Distributor
- GIC ITS control
- GIC ITS translation
- GIC Redistributor
- GIC Virtual CPU interface
- GIC Virtual interface control
- MPAM.any
- PMU
- RAS
- Timer
In the AMU block:
| Offset | Name | Description |
|---|---|---|
| 0x000 + | AMEVCNTR0<n>[31:0] | Activity Monitors Event Counter Registers 0 |
| 0x004 + | AMEVCNTR0<n>[63:32] | Activity Monitors Event Counter Registers 0 |
| 0x100 + | AMEVCNTR1<n>[31:0] | Activity Monitors Event Counter Registers 1 |
| 0x104 + | AMEVCNTR1<n>[63:32] | Activity Monitors Event Counter Registers 1 |
| 0x400 + | AMEVTYPER0<n> | Activity Monitors Event Type Registers 0 |
| 0x480 + | AMEVTYPER1<n> | Activity Monitors Event Type Registers 1 |
| 0xC00 | AMCNTENSET0 | Activity Monitors Count Enable Set Register 0 |
| 0xC04 | AMCNTENSET1 | Activity Monitors Count Enable Set Register 1 |
| 0xC20 | AMCNTENCLR0 | Activity Monitors Count Enable Clear Register 0 |
| 0xC24 | AMCNTENCLR1 | Activity Monitors Count Enable Clear Register 1 |
| 0xCE0 | AMCGCR | Activity Monitors Counter Group Configuration Register |
| 0xE00 | AMCFGR | Activity Monitors Configuration Register |
| 0xE04 | AMCR | Activity Monitors Control Register |
| 0xE08 | AMIIDR | Activity Monitors Implementation Identification Register |
| 0xFA8 | AMDEVAFF0 | Activity Monitors Device Affinity Register 0 |
| 0xFAC | AMDEVAFF1 | Activity Monitors Device Affinity Register 1 |
| 0xFBC | AMDEVARCH | Activity Monitors Device Architecture Register |
| 0xFCC | AMDEVTYPE | Activity Monitors Device Type Register |
| 0xFD0 | AMPIDR4 | Activity Monitors Peripheral Identification Register 4 |
| 0xFE0 | AMPIDR0 | Activity Monitors Peripheral Identification Register 0 |
| 0xFE4 | AMPIDR1 | Activity Monitors Peripheral Identification Register 1 |
| 0xFE8 | AMPIDR2 | Activity Monitors Peripheral Identification Register 2 |
| 0xFEC | AMPIDR3 | Activity Monitors Peripheral Identification Register 3 |
| 0xFF0 | AMCIDR0 | Activity Monitors Component Identification Register 0 |
| 0xFF4 | AMCIDR1 | Activity Monitors Component Identification Register 1 |
| 0xFF8 | AMCIDR2 | Activity Monitors Component Identification Register 2 |
| 0xFFC | AMCIDR3 | Activity Monitors Component Identification Register 3 |
In the CTI block:
| Offset | Name | Description |
|---|---|---|
| 0x000 | CTICONTROL | CTI Control register |
| 0x010 | CTIINTACK | CTI Output Trigger Acknowledge register |
| 0x014 | CTIAPPSET | CTI Application Trigger Set register |
| 0x018 | CTIAPPCLEAR | CTI Application Trigger Clear register |
| 0x01C | CTIAPPPULSE | CTI Application Pulse register |
| 0x020 + | CTIINEN<n> | CTI Input Trigger to Output Channel Enable registers |
| 0x0A0 + | CTIOUTEN<n> | CTI Input Channel to Output Trigger Enable registers |
| 0x130 | CTITRIGINSTATUS | CTI Trigger In Status register |
| 0x134 | CTITRIGOUTSTATUS | CTI Trigger Out Status register |
| 0x138 | CTICHINSTATUS | CTI Channel In Status register |
| 0x13C | CTICHOUTSTATUS | CTI Channel Out Status register |
| 0x140 | CTIGATE | CTI Channel Gate Enable register |
| 0x144 | ASICCTL | CTI External Multiplexer Control register |
| 0x150 | CTIDEVCTL | CTI Device Control register |
| 0xF00 | CTIITCTRL | CTI Integration mode Control register |
| 0xFA0 | CTICLAIMSET | CTI Claim Tag Set register |
| 0xFA4 | CTICLAIMCLR | CTI Claim Tag Clear register |
| 0xFA8 | CTIDEVAFF0 | CTI Device Affinity register 0 |
| 0xFAC | CTIDEVAFF1 | CTI Device Affinity register 1 |
| 0xFB0 | CTILAR | CTI Lock Access Register |
| 0xFB4 | CTILSR | CTI Lock Status Register |
| 0xFB8 | CTIAUTHSTATUS | CTI Authentication Status register |
| 0xFBC | CTIDEVARCH | CTI Device Architecture register |
| 0xFC0 | CTIDEVID2 | CTI Device ID register 2 |
| 0xFC4 | CTIDEVID1 | CTI Device ID register 1 |
| 0xFC8 | CTIDEVID | CTI Device ID register 0 |
| 0xFCC | CTIDEVTYPE | CTI Device Type register |
| 0xFD0 | CTIPIDR4 | CTI Peripheral Identification Register 4 |
| 0xFE0 | CTIPIDR0 | CTI Peripheral Identification Register 0 |
| 0xFE4 | CTIPIDR1 | CTI Peripheral Identification Register 1 |
| 0xFE8 | CTIPIDR2 | CTI Peripheral Identification Register 2 |
| 0xFEC | CTIPIDR3 | CTI Peripheral Identification Register 3 |
| 0xFF0 | CTICIDR0 | CTI Component Identification Register 0 |
| 0xFF4 | CTICIDR1 | CTI Component Identification Register 1 |
| 0xFF8 | CTICIDR2 | CTI Component Identification Register 2 |
| 0xFFC | CTICIDR3 | CTI Component Identification Register 3 |
In the Debug block:
| Offset | Name | Description |
|---|---|---|
| 0x020 | EDESR | External Debug Event Status Register |
| 0x024 | EDECR | External Debug Execution Control Register |
| 0x030 | EDWAR[31:0] | External Debug Watchpoint Address Register |
| 0x034 | EDWAR[63:32] | External Debug Watchpoint Address Register |
| 0x080 | DBGDTRRX_EL0 | Debug Data Transfer Register, Receive |
| 0x084 | EDITR | External Debug Instruction Transfer Register |
| 0x088 | EDSCR | External Debug Status and Control Register |
| 0x08C | DBGDTRTX_EL0 | Debug Data Transfer Register, Transmit |
| 0x090 | EDRCR | External Debug Reserve Control Register |
| 0x094 | EDACR | External Debug Auxiliary Control Register |
| 0x098 | EDECCR | External Debug Exception Catch Control Register |
| 0x0A0 | EDPCSR[31:0] | External Debug Program Counter Sample Register |
| 0x0A4 | EDCIDSR | External Debug Context ID Sample Register |
| 0x0A8 | EDVIDSR | External Debug Virtual Context Sample Register |
| 0x0AC | EDPCSR[63:32] | External Debug Program Counter Sample Register |
| 0x300 | OSLAR_EL1 | OS Lock Access Register |
| 0x310 | EDPRCR | External Debug Power/Reset Control Register |
| 0x314 | EDPRSR | External Debug Processor Status Register |
| 0x400 + | DBGBVR<n>_EL1[63:0] | Debug Breakpoint Value Registers |
| 0x408 + | DBGBCR<n>_EL1 | Debug Breakpoint Control Registers |
| 0x800 + | DBGWVR<n>_EL1[63:0] | Debug Watchpoint Value Registers |
| 0x808 + | DBGWCR<n>_EL1 | Debug Watchpoint Control Registers |
| 0xD00 | MIDR_EL1 | Main ID Register |
| 0xD20 | EDPFR[31:0] | External Debug Processor Feature Register |
| 0xD24 | EDPFR[63:32] | External Debug Processor Feature Register |
| 0xD28 | EDDFR[31:0] | External Debug Feature Register |
| 0xD2C | EDDFR[63:32] | External Debug Feature Register |
| 0xD60 | EDAA32PFR | External Debug AArch32 Processor Feature Register |
| 0xF00 | EDITCTRL | External Debug Integration mode Control register |
| 0xFA0 | DBGCLAIMSET_EL1 | Debug Claim Tag Set register |
| 0xFA4 | DBGCLAIMCLR_EL1 | Debug Claim Tag Clear register |
| 0xFA8 | EDDEVAFF0 | External Debug Device Affinity register 0 |
| 0xFAC | EDDEVAFF1 | External Debug Device Affinity register 1 |
| 0xFB0 | EDLAR | External Debug Lock Access Register |
| 0xFB4 | EDLSR | External Debug Lock Status Register |
| 0xFB8 | DBGAUTHSTATUS_EL1 | Debug Authentication Status register |
| 0xFBC | EDDEVARCH | External Debug Device Architecture register |
| 0xFC0 | EDDEVID2 | External Debug Device ID register 2 |
| 0xFC4 | EDDEVID1 | External Debug Device ID register 1 |
| 0xFC8 | EDDEVID | External Debug Device ID register 0 |
| 0xFCC | EDDEVTYPE | External Debug Device Type register |
| 0xFD0 | EDPIDR4 | External Debug Peripheral Identification Register 4 |
| 0xFE0 | EDPIDR0 | External Debug Peripheral Identification Register 0 |
| 0xFE4 | EDPIDR1 | External Debug Peripheral Identification Register 1 |
| 0xFE8 | EDPIDR2 | External Debug Peripheral Identification Register 2 |
| 0xFEC | EDPIDR3 | External Debug Peripheral Identification Register 3 |
| 0xFF0 | EDCIDR0 | External Debug Component Identification Register 0 |
| 0xFF4 | EDCIDR1 | External Debug Component Identification Register 1 |
| 0xFF8 | EDCIDR2 | External Debug Component Identification Register 2 |
| 0xFFC | EDCIDR3 | External Debug Component Identification Register 3 |
In the GIC CPU interface block:
| Offset | Name | Description |
|---|---|---|
| 0x0000 | GICC_CTLR | CPU Interface Control Register |
| 0x0004 | GICC_PMR | CPU Interface Priority Mask Register |
| 0x0008 | GICC_BPR | CPU Interface Binary Point Register |
| 0x000C | GICC_IAR | CPU Interface Interrupt Acknowledge Register |
| 0x0010 | GICC_EOIR | CPU Interface End Of Interrupt Register |
| 0x0014 | GICC_RPR | CPU Interface Running Priority Register |
| 0x0018 | GICC_HPPIR | CPU Interface Highest Priority Pending Interrupt Register |
| 0x001C | GICC_ABPR | CPU Interface Aliased Binary Point Register |
| 0x0020 | GICC_AIAR | CPU Interface Aliased Interrupt Acknowledge Register |
| 0x0024 | GICC_AEOIR | CPU Interface Aliased End Of Interrupt Register |
| 0x0028 | GICC_AHPPIR | CPU Interface Aliased Highest Priority Pending Interrupt Register |
| 0x002C | GICC_STATUSR | CPU Interface Status Register |
| 0x002C | GICC_STATUSR | CPU Interface Status Register |
| 0x00D0 + | GICC_APR<n> | CPU Interface Active Priorities Registers |
| 0x00E0 + | GICC_NSAPR<n> | CPU Interface Non-secure Active Priorities Registers |
| 0x00FC | GICC_IIDR | CPU Interface Identification Register |
| 0x1000 | GICC_DIR | CPU Interface Deactivate Interrupt Register |
In the GIC Distributor block:
| Offset | Name | Description |
|---|---|---|
| 0x0000 | GICD_CTLR | Distributor Control Register |
| 0x0004 | GICD_TYPER | Interrupt Controller Type Register |
| 0x0008 | GICD_IIDR | Distributor Implementer Identification Register |
| 0x0010 | GICD_STATUSR | Error Reporting Status Register |
| 0x0010 | GICD_STATUSR | Error Reporting Status Register |
| 0x0040 | GICD_SETSPI_NSR | Set Non-secure SPI Pending Register |
| 0x0048 | GICD_CLRSPI_NSR | Clear Non-secure SPI Pending Register |
| 0x0050 | GICD_SETSPI_SR | Set Secure SPI Pending Register |
| 0x0058 | GICD_CLRSPI_SR | Clear Secure SPI Pending Register |
| 0x0080 + | GICD_IGROUPR<n> | Interrupt Group Registers |
| 0x0100 + | GICD_ISENABLER<n> | Interrupt Set-Enable Registers |
| 0x0180 + | GICD_ICENABLER<n> | Interrupt Clear-Enable Registers |
| 0x0200 + | GICD_ISPENDR<n> | Interrupt Set-Pending Registers |
| 0x0280 + | GICD_ICPENDR<n> | Interrupt Clear-Pending Registers |
| 0x0300 + | GICD_ISACTIVER<n> | Interrupt Set-Active Registers |
| 0x0380 + | GICD_ICACTIVER<n> | Interrupt Clear-Active Registers |
| 0x0400 + | GICD_IPRIORITYR<n> | Interrupt Priority Registers |
| 0x0800 + | GICD_ITARGETSR<n> | Interrupt Processor Targets Registers |
| 0x0C00 + | GICD_ICFGR<n> | Interrupt Configuration Registers |
| 0x0D00 + | GICD_IGRPMODR<n> | Interrupt Group Modifier Registers |
| 0x0E00 + | GICD_NSACR<n> | Non-secure Access Control Registers |
| 0x0F00 | GICD_SGIR | Software Generated Interrupt Register |
| 0x0F10 + | GICD_CPENDSGIR<n> | SGI Clear-Pending Registers |
| 0x0F20 + | GICD_SPENDSGIR<n> | SGI Set-Pending Registers |
| 0x1000 + | GICD_IGROUPR<n>E | Interrupt Group Registers (extended SPI range) |
| 0x1200 + | GICD_ISENABLER<n>E | Interrupt Set-Enable Registers |
| 0x1400 + | GICD_ICENABLER<n>E | Interrupt Clear-Enable Registers |
| 0x1600 + | GICD_ISPENDR<n>E | Interrupt Set-Pending Registers (extended SPI range) |
| 0x1800 + | GICD_ICPENDR<n>E | Interrupt Clear-Pending Registers (extended SPI range) |
| 0x1A00 + | GICD_ISACTIVER<n>E | Interrupt Set-Active Registers (extended SPI range) |
| 0x1C00 + | GICD_ICACTIVER<n>E | Interrupt Clear-Active Registers (extended SPI range) |
| 0x1E00 + | GICD_ICFGR<n>E | Interrupt Configuration Registers (Extended SPI Range) |
| 0x2000 + | GICD_IPRIORITYR<n>E | Holds the priority of the corresponding interrupt for each extended SPI supported by the GIC. |
| 0x3000 + | GICD_IGRPMODR<n>E | Interrupt Group Modifier Registers (extended SPI range) |
| 0x3600 + | GICD_NSACR<n>E | Non-secure Access Control Registers |
| 0x6000 + | GICD_IROUTER<n> | Interrupt Routing Registers |
| 0x8000 + | GICD_IROUTER<n>E | Interrupt Routing Registers (Extended SPI Range) |
In the GIC ITS control block:
| Offset | Name | Description |
|---|---|---|
| 0x0000 | GITS_CTLR | ITS Control Register |
| 0x0004 | GITS_IIDR | ITS Identification Register |
| 0x0008 | GITS_TYPER | ITS Type Register |
| 0x0010 | GITS_MPAMIDR | Report maximum PARTID and PMG Register |
| 0x0014 | GITS_PARTIDR | Set PARTID and PMG Register |
| 0x0080 | GITS_CBASER | ITS Command Queue Descriptor |
| 0x0088 | GITS_CWRITER | ITS Write Register |
| 0x0090 | GITS_CREADR | ITS Read Register |
| 0x0100 + | GITS_BASER<n> | ITS Translation Table Descriptors |
In the GIC ITS translation block:
| Offset | Name | Description |
|---|---|---|
| 0x0040 | GITS_TRANSLATER | ITS Translation Register |
In the GIC Redistributor block:
| Frame | Offset | Name | Description |
|---|---|---|---|
| RD_base | 0x0000 | GICR_CTLR | Redistributor Control Register |
| RD_base | 0x0004 | GICR_IIDR | Redistributor Implementer Identification Register |
| RD_base | 0x0008 | GICR_TYPER | Redistributor Type Register |
| RD_base | 0x0010 | GICR_STATUSR | Error Reporting Status Register |
| RD_base | 0x0010 | GICR_STATUSR | Error Reporting Status Register |
| RD_base | 0x0014 | GICR_WAKER | Redistributor Wake Register |
| RD_base | 0x0018 | GICR_MPAMIDR | Report maximum PARTID and PMG Register |
| RD_base | 0x001C | GICR_PARTIDR | Set PARTID and PMG Register |
| RD_base | 0x0040 | GICR_SETLPIR | Set LPI Pending Register |
| RD_base | 0x0048 | GICR_CLRLPIR | Clear LPI Pending Register |
| RD_base | 0x0070 | GICR_PROPBASER | Redistributor Properties Base Address Register |
| RD_base | 0x0078 | GICR_PENDBASER | Redistributor LPI Pending Table Base Address Register |
| RD_base | 0x00A0 | GICR_INVLPIR | Redistributor Invalidate LPI Register |
| RD_base | 0x00B0 | GICR_INVALLR | Redistributor Invalidate All Register |
| RD_base | 0x00C0 | GICR_SYNCR | Redistributor Synchronize Register |
| SGI_base | 0x0080 | GICR_IGROUPR0 | Interrupt Group Register 0 |
| SGI_base | 0x0080 + | GICR_IGROUPR<n>E | Interrupt Group Registers |
| SGI_base | 0x0100 | GICR_ISENABLER0 | Interrupt Set-Enable Register 0 |
| SGI_base | 0x0100 + | GICR_ISENABLER<n>E | Interrupt Set-Enable Registers |
| SGI_base | 0x0180 | GICR_ICENABLER0 | Interrupt Clear-Enable Register 0 |
| SGI_base | 0x0180 + | GICR_ICENABLER<n>E | Interrupt Clear-Enable Registers |
| SGI_base | 0x0200 | GICR_ISPENDR0 | Interrupt Set-Pending Register 0 |
| SGI_base | 0x0200 + | GICR_ISPENDR<n>E | Interrupt Set-Pending Registers |
| SGI_base | 0x0280 | GICR_ICPENDR0 | Interrupt Clear-Pending Register 0 |
| SGI_base | 0x0280 + | GICR_ICPENDR<n>E | Interrupt Clear-Pending Registers |
| SGI_base | 0x0300 | GICR_ISACTIVER0 | Interrupt Set-Active Register 0 |
| SGI_base | 0x0300 + | GICR_ISACTIVER<n>E | Interrupt Set-Active Registers |
| SGI_base | 0x0380 | GICR_ICACTIVER0 | Interrupt Clear-Active Register 0 |
| SGI_base | 0x0380 + | GICR_ICACTIVER<n>E | Interrupt Clear-Active Registers |
| SGI_base | 0x0400 + | GICR_IPRIORITYR<n> | Interrupt Priority Registers |
| SGI_base | 0x0400 + | GICR_IPRIORITYR<n>E | Interrupt Priority Registers (extended PPI range) |
| SGI_base | 0x0C00 | GICR_ICFGR0 | Interrupt Configuration Register 0 |
| SGI_base | 0x0C00 + | GICR_ICFGR<n>E | Interrupt configuration registers |
| SGI_base | 0x0C04 | GICR_ICFGR1 | Interrupt Configuration Register 1 |
| SGI_base | 0x0D00 | GICR_IGRPMODR0 | Interrupt Group Modifier Register 0 |
| SGI_base | 0x0D00 + | GICR_IGRPMODR<n>E | Interrupt Group Modifier Registers |
| SGI_base | 0x0E00 | GICR_NSACR | Non-secure Access Control Register |
| VLPI_base | 0x0070 | GICR_VPROPBASER | Virtual Redistributor Properties Base Address Register |
| VLPI_base | 0x0078 | GICR_VPENDBASER | Virtual Redistributor LPI Pending Table Base Address Register |
In the GIC Virtual CPU interface block:
| Offset | Name | Description |
|---|---|---|
| 0x0000 | GICV_CTLR | Virtual Machine Control Register |
| 0x0004 | GICV_PMR | Virtual Machine Priority Mask Register |
| 0x0008 | GICV_BPR | Virtual Machine Binary Point Register |
| 0x000C | GICV_IAR | Virtual Machine Interrupt Acknowledge Register |
| 0x0010 | GICV_EOIR | Virtual Machine End Of Interrupt Register |
| 0x0014 | GICV_RPR | Virtual Machine Running Priority Register |
| 0x0018 | GICV_HPPIR | Virtual Machine Highest Priority Pending Interrupt Register |
| 0x001C | GICV_ABPR | Virtual Machine Aliased Binary Point Register |
| 0x0020 | GICV_AIAR | Virtual Machine Aliased Interrupt Acknowledge Register |
| 0x0024 | GICV_AEOIR | Virtual Machine Aliased End Of Interrupt Register |
| 0x0028 | GICV_AHPPIR | Virtual Machine Aliased Highest Priority Pending Interrupt Register |
| 0x002C | GICV_STATUSR | Virtual Machine Error Reporting Status Register |
| 0x00D0 + | GICV_APR<n> | Virtual Machine Active Priorities Registers |
| 0x00FC | GICV_IIDR | Virtual Machine CPU Interface Identification Register |
| 0x1000 | GICV_DIR | Virtual Machine Deactivate Interrupt Register |
In the GIC Virtual interface control block:
| Offset | Name | Description |
|---|---|---|
| 0x0000 | GICH_HCR | Hypervisor Control Register |
| 0x0004 | GICH_VTR | Virtual Type Register |
| 0x0008 | GICH_VMCR | Virtual Machine Control Register |
| 0x0010 | GICH_MISR | Maintenance Interrupt Status Register |
| 0x0020 | GICH_EISR | End Interrupt Status Register |
| 0x0030 | GICH_ELRSR | Empty List Register Status Register |
| 0x00F0 + | GICH_APR<n> | Active Priorities Registers |
| 0x0100 + | GICH_LR<n> | List Registers |
In the MPAM.any block:
| Frame | Offset | Name | Description |
|---|---|---|---|
| MPAMF_BASE_ns | 0x0000 | MPAMF_IDR | MPAM Features Identification Register |
| MPAMF_BASE_ns | 0x0018 | MPAMF_IIDR | MPAM Implemenation Identification Register |
| MPAMF_BASE_ns | 0x0020 | MPAMF_AIDR | MPAM Architecture Identification Register |
| MPAMF_BASE_ns | 0x0028 | MPAMF_IMPL_IDR | MPAM Implementation-Specific Partitioning Feature Identification Register |
| MPAMF_BASE_ns | 0x0030 | MPAMF_CPOR_IDR | MPAM Features Cache Portion Partitioning ID register |
| MPAMF_BASE_ns | 0x0038 | MPAMF_CCAP_IDR | MPAM Features Cache Capacity Partitioning ID register |
| MPAMF_BASE_ns | 0x0040 | MPAMF_MBW_IDR | MPAM Memory Bandwidth Partitioning Identification Register |
| MPAMF_BASE_ns | 0x0048 | MPAMF_PRI_IDR | MPAM Priority Partitioning Identification Register |
| MPAMF_BASE_ns | 0x0050 | MPAMF_PARTID_NRW_IDR | MPAM PARTID Narrowing ID register |
| MPAMF_BASE_ns | 0x0080 | MPAMF_MSMON_IDR | MPAM Resource Monitoring Identification Register |
| MPAMF_BASE_ns | 0x0088 | MPAMF_CSUMON_IDR | MPAM Features Cache Storage Usage Monitoring ID register |
| MPAMF_BASE_ns | 0x0090 | MPAMF_MBWUMON_IDR | MPAM Features Memory Bandwidth Usage Monitoring ID register |
| MPAMF_BASE_ns | 0x00F0 | MPAMF_ECR | MPAM Error Control Register |
| MPAMF_BASE_ns | 0x00F8 | MPAMF_ESR | MPAM Error Status Register |
| MPAMF_BASE_ns | 0x0100 | MPAMCFG_PART_SEL | MPAM Partion Configuration Selection Register |
| MPAMF_BASE_ns | 0x0108 | MPAMCFG_CMAX | MPAM Cache Maximum Capacity Partition Configuration Register |
| MPAMF_BASE_ns | 0x0200 | MPAMCFG_MBW_MIN | MPAM Cache Maximum Capacity Partition Configuration Register |
| MPAMF_BASE_ns | 0x0208 | MPAMCFG_MBW_MAX | MPAM Memory Bandwidth Maximum Partition Configuration Register |
| MPAMF_BASE_ns | 0x0220 | MPAMCFG_MBW_WINWD | MPAM Memory Bandwidth Partitioning Window Width Configuration Register |
| MPAMF_BASE_ns | 0x0400 | MPAMCFG_PRI | MPAM Priority Partition Configuration Register |
| MPAMF_BASE_ns | 0x0500 | MPAMCFG_MBW_PROP | MPAM Memory Bandwidth Proportional Stride Partition Configuration Register |
| MPAMF_BASE_ns | 0x0600 | MPAMCFG_INTPARTID | MPAM Internal PARTID Narrowing Configuration Register |
| MPAMF_BASE_ns | 0x0800 | MSMON_CFG_MON_SEL | MPAM Partion Configuration Selection Register |
| MPAMF_BASE_ns | 0x0808 | MSMON_CAPT_EVNT | MPAM Capture Event Generation Register |
| MPAMF_BASE_ns | 0x0810 | MSMON_CFG_CSU_FLT | MPAM Memory System Monitor Configure Cache Storage Usage Monitor Filter Register |
| MPAMF_BASE_ns | 0x0818 | MSMON_CFG_CSU_CTL | MPAM Memory System Monitor Configure Cache Storage Usage Monitor Control Register |
| MPAMF_BASE_ns | 0x0820 | MSMON_CFG_MBWU_FLT | MPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Filter Register |
| MPAMF_BASE_ns | 0x0828 | MSMON_CFG_MBWU_CTL | MPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Control Register |
| MPAMF_BASE_ns | 0x0840 | MSMON_CSU | MPAM Cache Storage Usage Monitor Register |
| MPAMF_BASE_ns | 0x0848 | MSMON_CSU_CAPTURE | MPAM Cache Storage Usage Monitor Capture Register |
| MPAMF_BASE_ns | 0x0860 | MSMON_MBWU | MPAM Memory Bandwdith Usage Monitor Register |
| MPAMF_BASE_ns | 0x0868 | MSMON_MBWU_CAPTURE | MPAM Memory Bandwidth Usage Monitor Capture Register |
| MPAMF_BASE_ns | 0x1000 | MPAMCFG_CPBM | MPAM Cache Portion Bitmap Partition Configuration Register |
| MPAMF_BASE_ns | 0x2000 | MPAMCFG_MBW_PBM | MPAM Bandwidth Portion Bitmap Parition Configuration Register |
| MPAMF_BASE_s | 0x0000 | MPAMF_IDR | MPAM Features Identification Register |
| MPAMF_BASE_s | 0x0008 | MPAMF_SIDR | MPAM Features Secure Identification Register |
| MPAMF_BASE_s | 0x0018 | MPAMF_IIDR | MPAM Implemenation Identification Register |
| MPAMF_BASE_s | 0x0020 | MPAMF_AIDR | MPAM Architecture Identification Register |
| MPAMF_BASE_s | 0x0028 | MPAMF_IMPL_IDR | MPAM Implementation-Specific Partitioning Feature Identification Register |
| MPAMF_BASE_s | 0x0030 | MPAMF_CPOR_IDR | MPAM Features Cache Portion Partitioning ID register |
| MPAMF_BASE_s | 0x0038 | MPAMF_CCAP_IDR | MPAM Features Cache Capacity Partitioning ID register |
| MPAMF_BASE_s | 0x0040 | MPAMF_MBW_IDR | MPAM Memory Bandwidth Partitioning Identification Register |
| MPAMF_BASE_s | 0x0048 | MPAMF_PRI_IDR | MPAM Priority Partitioning Identification Register |
| MPAMF_BASE_s | 0x0050 | MPAMF_PARTID_NRW_IDR | MPAM PARTID Narrowing ID register |
| MPAMF_BASE_s | 0x0080 | MPAMF_MSMON_IDR | MPAM Resource Monitoring Identification Register |
| MPAMF_BASE_s | 0x0088 | MPAMF_CSUMON_IDR | MPAM Features Cache Storage Usage Monitoring ID register |
| MPAMF_BASE_s | 0x0090 | MPAMF_MBWUMON_IDR | MPAM Features Memory Bandwidth Usage Monitoring ID register |
| MPAMF_BASE_s | 0x00F0 | MPAMF_ECR | MPAM Error Control Register |
| MPAMF_BASE_s | 0x00F8 | MPAMF_ESR | MPAM Error Status Register |
| MPAMF_BASE_s | 0x0100 | MPAMCFG_PART_SEL | MPAM Partion Configuration Selection Register |
| MPAMF_BASE_s | 0x0108 | MPAMCFG_CMAX | MPAM Cache Maximum Capacity Partition Configuration Register |
| MPAMF_BASE_s | 0x0200 | MPAMCFG_MBW_MIN | MPAM Cache Maximum Capacity Partition Configuration Register |
| MPAMF_BASE_s | 0x0208 | MPAMCFG_MBW_MAX | MPAM Memory Bandwidth Maximum Partition Configuration Register |
| MPAMF_BASE_s | 0x0220 | MPAMCFG_MBW_WINWD | MPAM Memory Bandwidth Partitioning Window Width Configuration Register |
| MPAMF_BASE_s | 0x0400 | MPAMCFG_PRI | MPAM Priority Partition Configuration Register |
| MPAMF_BASE_s | 0x0500 | MPAMCFG_MBW_PROP | MPAM Memory Bandwidth Proportional Stride Partition Configuration Register |
| MPAMF_BASE_s | 0x0600 | MPAMCFG_INTPARTID | MPAM Internal PARTID Narrowing Configuration Register |
| MPAMF_BASE_s | 0x0800 | MSMON_CFG_MON_SEL | MPAM Partion Configuration Selection Register |
| MPAMF_BASE_s | 0x0808 | MSMON_CAPT_EVNT | MPAM Capture Event Generation Register |
| MPAMF_BASE_s | 0x0810 | MSMON_CFG_CSU_FLT | MPAM Memory System Monitor Configure Cache Storage Usage Monitor Filter Register |
| MPAMF_BASE_s | 0x0818 | MSMON_CFG_CSU_CTL | MPAM Memory System Monitor Configure Cache Storage Usage Monitor Control Register |
| MPAMF_BASE_s | 0x0820 | MSMON_CFG_MBWU_FLT | MPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Filter Register |
| MPAMF_BASE_s | 0x0828 | MSMON_CFG_MBWU_CTL | MPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Control Register |
| MPAMF_BASE_s | 0x0840 | MSMON_CSU | MPAM Cache Storage Usage Monitor Register |
| MPAMF_BASE_s | 0x0848 | MSMON_CSU_CAPTURE | MPAM Cache Storage Usage Monitor Capture Register |
| MPAMF_BASE_s | 0x0860 | MSMON_MBWU | MPAM Memory Bandwdith Usage Monitor Register |
| MPAMF_BASE_s | 0x0868 | MSMON_MBWU_CAPTURE | MPAM Memory Bandwidth Usage Monitor Capture Register |
| MPAMF_BASE_s | 0x1000 | MPAMCFG_CPBM | MPAM Cache Portion Bitmap Partition Configuration Register |
| MPAMF_BASE_s | 0x2000 | MPAMCFG_MBW_PBM | MPAM Bandwidth Portion Bitmap Parition Configuration Register |
In the PMU block:
| Offset | Name | Description |
|---|---|---|
| 0x000 + | PMEVCNTR<n>_EL0 | Performance Monitors Event Count Registers |
| 0x0F8 | PMCCNTR_EL0[31:0] | Performance Monitors Cycle Counter |
| 0x0FC | PMCCNTR_EL0[63:32] | Performance Monitors Cycle Counter |
| 0x200 | PMPCSR[31:0] | Program Counter Sample Register |
| 0x204 | PMPCSR[63:32] | Program Counter Sample Register |
| 0x208 | PMCID1SR | CONTEXTIDR_EL1 Sample Register |
| 0x20C | PMVIDSR | VMID Sample Register |
| 0x220 | PMPCSR[31:0] | Program Counter Sample Register |
| 0x224 | PMPCSR[63:32] | Program Counter Sample Register |
| 0x228 | PMCID1SR | CONTEXTIDR_EL1 Sample Register |
| 0x22C | PMCID2SR | CONTEXTIDR_EL2 Sample Register |
| 0x400 + | PMEVTYPER<n>_EL0 | Performance Monitors Event Type Registers |
| 0x47C | PMCCFILTR_EL0 | Performance Monitors Cycle Counter Filter Register |
| 0xC00 | PMCNTENSET_EL0 | Performance Monitors Count Enable Set register |
| 0xC20 | PMCNTENCLR_EL0 | Performance Monitors Count Enable Clear register |
| 0xC40 | PMINTENSET_EL1 | Performance Monitors Interrupt Enable Set register |
| 0xC60 | PMINTENCLR_EL1 | Performance Monitors Interrupt Enable Clear register |
| 0xC80 | PMOVSCLR_EL0 | Performance Monitors Overflow Flag Status Clear register |
| 0xCA0 | PMSWINC_EL0 | Performance Monitors Software Increment register |
| 0xCC0 | PMOVSSET_EL0 | Performance Monitors Overflow Flag Status Set register |
| 0xE00 | PMCFGR | Performance Monitors Configuration Register |
| 0xE04 | PMCR_EL0 | Performance Monitors Control Register |
| 0xE20 | PMCEID0 | Performance Monitors Common Event Identification register 0 |
| 0xE24 | PMCEID1 | Performance Monitors Common Event Identification register 1 |
| 0xE28 | PMCEID2 | Performance Monitors Common Event Identification register 2 |
| 0xE2C | PMCEID3 | Performance Monitors Common Event Identification register 3 |
| 0xE40 | PMMIR | Performance Monitors Machine Identification Register |
| 0xF00 | PMITCTRL | Performance Monitors Integration mode Control register |
| 0xFA8 | PMDEVAFF0 | Performance Monitors Device Affinity register 0 |
| 0xFAC | PMDEVAFF1 | Performance Monitors Device Affinity register 1 |
| 0xFB0 | PMLAR | Performance Monitors Lock Access Register |
| 0xFB4 | PMLSR | Performance Monitors Lock Status Register |
| 0xFB8 | PMAUTHSTATUS | Performance Monitors Authentication Status register |
| 0xFBC | PMDEVARCH | Performance Monitors Device Architecture register |
| 0xFC8 | PMDEVID | Performance Monitors Device ID register |
| 0xFCC | PMDEVTYPE | Performance Monitors Device Type register |
| 0xFD0 | PMPIDR4 | Performance Monitors Peripheral Identification Register 4 |
| 0xFE0 | PMPIDR0 | Performance Monitors Peripheral Identification Register 0 |
| 0xFE4 | PMPIDR1 | Performance Monitors Peripheral Identification Register 1 |
| 0xFE8 | PMPIDR2 | Performance Monitors Peripheral Identification Register 2 |
| 0xFEC | PMPIDR3 | Performance Monitors Peripheral Identification Register 3 |
| 0xFF0 | PMCIDR0 | Performance Monitors Component Identification Register 0 |
| 0xFF4 | PMCIDR1 | Performance Monitors Component Identification Register 1 |
| 0xFF8 | PMCIDR2 | Performance Monitors Component Identification Register 2 |
| 0xFFC | PMCIDR3 | Performance Monitors Component Identification Register 3 |
In the RAS block:
| Offset | Name | Description |
|---|---|---|
| 0x000 + | ERR<n>FR | Error Record Feature Register |
| 0x008 + | ERR<n>CTLR | Error Record Control Register |
| 0x010 + | ERR<n>STATUS | Error Record Primary Status Register |
| 0x018 + | ERR<n>ADDR | Error Record Address Register |
| 0x020 + | ERR<n>MISC0 | Error Record Miscellaneous Register 0 |
| 0x028 + | ERR<n>MISC1 | Error Record Miscellaneous Register 1 |
| 0x030 + | ERR<n>MISC2 | Error Record Miscellaneous Register 2 |
| 0x038 + | ERR<n>MISC3 | Error Record Miscellaneous Register 3 |
| 0x800 + | ERR<n>PFGF | Pseudo-fault Generation Feature Register |
| 0x808 + | ERR<n>PFGCTL | Pseudo-fault Generation Control Register |
| 0x810 + | ERR<n>PFGCDN | Pseudo-fault Generation Countdown Register |
| 0xE00 | ERRGSR | Error Group Status Register |
| 0xE10 | ERRIIDR | Implementation Identification Register |
| 0xE80 | ERRFHICR0 | Fault-Handling Interrupt Configuration Register 0 |
| 0xE80 + | ERRIRQCR<n> | Generic Error Interrupt Configuration Register |
| 0xE88 | ERRFHICR1 | Fault-Handling Interrupt Configuration Register 1 |
| 0xE8C | ERRFHICR2 | Fault-Handling Interrupt Configuration Register 2 |
| 0xE90 | ERRERICR0 | Error Recovery Interrupt Configuration Register 0 |
| 0xE98 | ERRERICR1 | Error Recovery Interrupt Configuration Register 1 |
| 0xE9C | ERRERICR2 | Error Recovery Interrupt Configuration Register 2 |
| 0xEA0 | ERRCRICR0 | Critical Error Interrupt Configuration Register 0 |
| 0xEA8 | ERRCRICR1 | Critical Error Interrupt Configuration Register 1 |
| 0xEAC | ERRCRICR2 | Critical Error Interrupt Configuration Register 2 |
| 0xEF8 | ERRIRQSR | Error Interrupt Status Register |
| 0xFA8 | ERRDEVAFF | Device Affinity Register |
| 0xFBC | ERRDEVARCH | Device Architecture Register |
| 0xFC8 | ERRDEVID | Device Configuration Register |
| 0xFD0 | ERRPIDR4 | Peripheral Identification Register 4 |
| 0xFE0 | ERRPIDR0 | Peripheral Identification Register 0 |
| 0xFE4 | ERRPIDR1 | Peripheral Identification Register 1 |
| 0xFE8 | ERRPIDR2 | Peripheral Identification Register 2 |
| 0xFEC | ERRPIDR3 | Peripheral Identification Register 3 |
| 0xFF0 | ERRCIDR0 | Component Identification Register 0 |
| 0xFF4 | ERRCIDR1 | Component Identification Register 1 |
| 0xFF8 | ERRCIDR2 | Component Identification Register 2 |
| 0xFFC | ERRCIDR3 | Component Identification Register 3 |
In the Timer block:
| Frame | Offset | Name | Description |
|---|---|---|---|
| CNTBaseN | 0x000 | CNTPCT[31:0] | Counter-timer Physical Count |
| CNTBaseN | 0x004 | CNTPCT[63:32] | Counter-timer Physical Count |
| CNTBaseN | 0x008 | CNTVCT[31:0] | Counter-timer Virtual Count |
| CNTBaseN | 0x00C | CNTVCT[63:32] | Counter-timer Virtual Count |
| CNTBaseN | 0x010 | CNTFRQ | Counter-timer Frequency |
| CNTBaseN | 0x014 | CNTEL0ACR | Counter-timer EL0 Access Control Register |
| CNTBaseN | 0x018 | CNTVOFF[31:0] | Counter-timer Virtual Offset |
| CNTBaseN | 0x01C | CNTVOFF[63:32] | Counter-timer Virtual Offset |
| CNTBaseN | 0x020 | CNTP_CVAL[31:0] | Counter-timer Physical Timer CompareValue |
| CNTBaseN | 0x024 | CNTP_CVAL[63:32] | Counter-timer Physical Timer CompareValue |
| CNTBaseN | 0x028 | CNTP_TVAL | Counter-timer Physical Timer TimerValue |
| CNTBaseN | 0x02C | CNTP_CTL | Counter-timer Physical Timer Control |
| CNTBaseN | 0x030 | CNTV_CVAL[31:0] | Counter-timer Virtual Timer CompareValue |
| CNTBaseN | 0x034 | CNTV_CVAL[63:32] | Counter-timer Virtual Timer CompareValue |
| CNTBaseN | 0x038 | CNTV_TVAL | Counter-timer Virtual Timer TimerValue |
| CNTBaseN | 0x03C | CNTV_CTL | Counter-timer Virtual Timer Control |
| CNTBaseN | 0xFD0 + | CounterID<n> | Counter ID registers |
| CNTCTLBase | 0x000 | CNTFRQ | Counter-timer Frequency |
| CNTCTLBase | 0x004 | CNTNSAR | Counter-timer Non-secure Access Register |
| CNTCTLBase | 0x008 | CNTTIDR | Counter-timer Timer ID Register |
| CNTCTLBase | 0x040 + | CNTACR<n> | Counter-timer Access Control Registers |
| CNTCTLBase | 0x080 + | CNTVOFF<n>[31:0] | Counter-timer Virtual Offsets |
| CNTCTLBase | 0x084 + | CNTVOFF<n>[63:32] | Counter-timer Virtual Offsets |
| CNTCTLBase | 0xFD0 + | CounterID<n> | Counter ID registers |
| CNTControlBase | 0x000 | CNTCR | Counter Control Register |
| CNTControlBase | 0x004 | CNTSR | Counter Status Register |
| CNTControlBase | 0x008 | CNTCV[63:0] | Counter Count Value register |
| CNTControlBase | 0x020 | CNTFID0 | Counter Frequency ID |
| CNTControlBase | 0x020 + | CNTFID<n> | Counter Frequency IDs, n > 0 |
| CNTControlBase | 0x10 | CNTSCR | Counter Scale Register |
| CNTControlBase | 0x1C | CNTID | Counter Identification Register |
| CNTControlBase | 0xFD0 + | CounterID<n> | Counter ID registers |
| CNTEL0BaseN | 0x000 | CNTPCT[31:0] | Counter-timer Physical Count |
| CNTEL0BaseN | 0x004 | CNTPCT[63:32] | Counter-timer Physical Count |
| CNTEL0BaseN | 0x008 | CNTVCT[31:0] | Counter-timer Virtual Count |
| CNTEL0BaseN | 0x00C | CNTVCT[63:32] | Counter-timer Virtual Count |
| CNTEL0BaseN | 0x010 | CNTFRQ | Counter-timer Frequency |
| CNTEL0BaseN | 0x020 | CNTP_CVAL[31:0] | Counter-timer Physical Timer CompareValue |
| CNTEL0BaseN | 0x024 | CNTP_CVAL[63:32] | Counter-timer Physical Timer CompareValue |
| CNTEL0BaseN | 0x028 | CNTP_TVAL | Counter-timer Physical Timer TimerValue |
| CNTEL0BaseN | 0x02C | CNTP_CTL | Counter-timer Physical Timer Control |
| CNTEL0BaseN | 0x030 | CNTV_CVAL[31:0] | Counter-timer Virtual Timer CompareValue |
| CNTEL0BaseN | 0x034 | CNTV_CVAL[63:32] | Counter-timer Virtual Timer CompareValue |
| CNTEL0BaseN | 0x038 | CNTV_TVAL | Counter-timer Virtual Timer TimerValue |
| CNTEL0BaseN | 0x03C | CNTV_CTL | Counter-timer Virtual Timer Control |
| CNTEL0BaseN | 0xFD0 + | CounterID<n> | Counter ID registers |
| CNTReadBase | 0x000 | CNTCV[63:0] | Counter Count Value register |
| CNTReadBase | 0xFD0 + | CounterID<n> | Counter ID registers |