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AMCIDR3, Activity Monitors Component Identification Register 3

The AMCIDR3 characteristics are:

Purpose

Provides information to identify an activity monitors component.

For more information, see About the Component identification scheme in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

Configuration

The power domain of AMCIDR3 is IMPLEMENTATION DEFINED.

Implementation of this register is OPTIONAL.

This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMCIDR3 are RES0.

Attributes

AMCIDR3 is a 32-bit register.

Field descriptions

The AMCIDR3 bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000000PRMBL_3

Bits [31:8]

Reserved, RES0.

PRMBL_3, bits [7:0]

Preamble. Reads as 0xB1.

Accessing the AMCIDR3

AMCIDR3 can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
AMU0xFFCAMCIDR3

Access on this interface is RO.



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