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AMCR, Activity Monitors Control Register

The AMCR characteristics are:

Purpose

Global control register for the activity monitors implementation. AMCR is applicable to both the architected and the auxiliary counter groups.

Configuration

External register AMCR bits [31:0] are architecturally mapped to AArch64 System register AMCR_EL0[31:0] .

External register AMCR bits [31:0] are architecturally mapped to AArch32 System register AMCR[31:0] .

The power domain of AMCR is IMPLEMENTATION DEFINED.

This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMCR are RES0.

Attributes

AMCR is a 32-bit register.

Field descriptions

The AMCR bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000HDBG0000000000

Bits [31:11]

Reserved, RES0.

HDBG, bit [10]

This bit controls whether activity monitor counting is halted when the PE is halted in Debug state.

HDBGMeaning
0b0

Activity monitors do not halt counting when the PE is halted in Debug state.

0b1

Activity monitors halt counting when the PE is halted in Debug state.

Bits [9:0]

Reserved, RAZ/WI.

Accessing the AMCR

AMCR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
AMU0xE04AMCR

Access on this interface is RO.



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