CNTFID<n>, Counter Frequency IDs, n > 0
The CNTFID<n> characteristics are:
Indicates alternative system counter update frequencies.
The power domain of CNTFID<n> is IMPLEMENTATION DEFINED.
If this register is implemented as an RW register, on a reset of the reset domain in which it is implemented, RW fields in this register reset to UNKNOWN values. The register is not affected by a reset of any other reset domain. For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in Chapter I1 of the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
The possible frequencies for the system counter are stored in the Frequency modes table as 32-bit words starting with the base frequency, CNTFID0, see 'The Frequency modes table' in Chapter I1 of the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
The number of CNTFID<n> registers is IMPLEMENTATION DEFINED, and the only required CNTFID<n> register is CNTFID0.
The final entry in the Frequency modes table must be followed by a 32-bit word of zero value, to mark the end of the table.
Typically, the Frequency modes table will be in read-only memory. However, a system implementation might use read/write memory for the table, and initialize the table entries as part of its start-up sequence.
If the Frequency modes table is in read/write memory, Arm strongly recommends that the table is not updated once the system is running.
CNTFID<n> is a 32-bit register.
The CNTFID<n> bit assignments are:
Frequency, bits [31:0]
A system counter update frequency, in Hz. Must be an exact divisor of the base frequency. Arm strongly recommends that all frequency values in the Frequency modes table are integer power-of-two divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the increment applied at each counter update is given by:
increment = (base frequency) / (selected frequency)
This field resets to an architecturally UNKNOWN value.
Accessing the CNTFID<n>
It is IMPLEMENTATION DEFINED whether this register is RO or RW
In a system that supports Secure and Non-secure memory maps the CNTControlBase frame, that includes these registers, is implemented only in the Secure memory map.
CNTFID<n> can be accessed through the memory-mapped interfaces:
|Timer||CNTControlBase||0x020 + 4n||CNTFID<n>|
Access on this interface is RO or RW.