CTILSR, CTI Lock Status Register
The CTILSR characteristics are:
Indicates the current status of the Software Lock for CTI registers.
CTILSR is in the Debug power domain. Some or all RW fields of this register have defined reset values. These apply only on an External debug reset. The register is not affected by a Warm reset and is not affected by a Cold reset.
CTILSR is RAZ if the Software Lock is not implemented and is RAZ for other accesses to the external debug interface.
The Software Lock provides a lock to prevent memory-mapped writes to the Cross-Trigger Interface registers. Use of this lock mechanism reduces the risk of accidental damage to the contents of the Cross-Trigger Interface registers. It does not, and cannot, prevent all accidental or malicious damage.
Software uses CTILAR to set or clear the lock, and CTILSR to check the current status of the lock.
CTILSR is a 32-bit register.
The CTILSR bit assignments are:
nTT, bit 
Not thirty-two bit access required. RAZ.
SLK, bit 
Software Lock status for this component. For an access to LSR that is not a memory-mapped access, or when the Software Lock is not implemented, this field is RES0.
For memory-mapped accesses when the Software Lock is implemented, possible values of this field are:
Lock clear. Writes are permitted to this component's registers.
Lock set. Writes to this component's registers are ignored, and reads have no side effects.
On a External debug reset, this field resets to 1.
SLI, bit 
Software Lock implemented. For an access to LSR that is not a memory-mapped access, this field is RAZ. For memory-mapped accesses, the value of this field is IMPLEMENTATION DEFINED. Permitted values are:
Software Lock not implemented or not memory-mapped access.
Software Lock implemented and memory-mapped access.
Accessing the CTILSR
CTILSR can be accessed through a memory-mapped access to the external debug interface:
Access on this interface is RO.