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EDESR, External Debug Event Status Register

The EDESR characteristics are:

Purpose

Indicates the status of internally pending Halting debug events.

Configuration

EDESR is in the Core power domain. Some or all RW fields of this register have defined reset values. The field descriptions identify when the reset values apply.

Attributes

EDESR is a 32-bit register.

Field descriptions

The EDESR bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000000000000000000000000SSRCOSUC

Bits [31:3]

Reserved, RES0.

SS, bit [2]

When ARMv8.3-DoPD is implemented:

Halting step debug event pending. Possible values of this field are:

SSMeaning
0b0

Reading this means that a Halting step debug event is not pending. Writing this means no action.

0b1

Reading this means that a Halting step debug event is pending. Writing this clears the pending Halting step debug event.

The following resets apply:

  • If the PE was stepping an instruction when a Warm reset occurs, the reset value of this bit is UNKNOWN, since it is not possible to determine whether this bit is updated before or after the Warm reset.

  • On a Cold reset, this field resets to 0.


Otherwise:

Halting step debug event pending. Possible values of this field are:

SSMeaning
0b0

Reading this means that a Halting step debug event is not pending. Writing this means no action.

0b1

Reading this means that a Halting step debug event is pending. Writing this clears the pending Halting step debug event.

On a Warm reset, this field resets to the value in EDECR.SS.

RC, bit [1]

Reset Catch debug event pending. Possible values of this field are:

RCMeaning
0b0

Reading this means that a Reset Catch debug event is not pending. Writing this means no action.

0b1

Reading this means that a Reset Catch debug event is pending. Writing this clears the pending Reset Catch debug event.

On a Warm reset, this field resets to the value in EDECR.RCE.

OSUC, bit [0]

OS Unlock Catch debug event pending. Possible values of this field are:

OSUCMeaning
0b0

Reading this means that an OS Unlock Catch debug event is not pending. Writing this means no action.

0b1

Reading this means that an OS Unlock Catch debug event is pending. Writing this clears the pending OS Unlock Catch debug event.

On a Warm reset, this field resets to 0.

Accessing the EDESR

If a request to clear a pending Halting debug event is received at or about the time when halting becomes allowed, it is CONSTRAINED UNPREDICTABLE whether the event is taken.

If Core power is removed while a Halting debug event is pending, it is lost. However, it might become pending again when the Core is powered back on and Cold reset.

EDESR can be accessed through the external debug interface:

ComponentOffsetInstance
Debug0x020EDESR

This interface is accessible as follows:

  • When IsCorePowered(), !DoubleLockStatus() and SoftwareLockStatus() access to this register is RO.
  • When IsCorePowered(), !DoubleLockStatus() and !SoftwareLockStatus() access to this register is RW.
  • Otherwise access to this register returns an Error.


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