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EDVIDSR, External Debug Virtual Context Sample Register

The EDVIDSR characteristics are:

Purpose

Contains sampled values captured on reading EDPCSR[31:0].

Configuration

EDVIDSR is in the Core power domain.

Fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

Implemented only if the OPTIONAL PC Sample-based Profiling Extension is implemented in the external debug registers space.

When the PC Sample-based Profiling Extension is implemented in the external debug registers space, if EL2 is not implemented and EL3 is not implemented, it is IMPLEMENTATION DEFINED whether EDVIDSR is implemented.

Note

ARMv8.2-PCSample implements the PC Sample-based Profiling Extension in the Performance Monitors registers space.

Attributes

If ARMv8.1-VHE is implemented, the format of this register differs depending on the value of EDSCR.SC2.

Field descriptions

The EDVIDSR bit assignments are:

When ARMv8.2-PCSample is implemented:
313029282726252423222120191817161514131211109876543210
00000000000000000000000000000000

Bits [31:0]

Reserved, RES0.

When ARMv8.1-VHE is not implemented:
313029282726252423222120191817161514131211109876543210
NSE2E3HV00000000000000000000VMID

NS, bit [31]

Non-secure state sample. Indicates the Security state associated with the most recent EDPCSR sample.

If EL3 is not implemented, this bit indicates the Effective value of SCR.NS.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

E2, bit [30]

Exception level 2 status sample. Indicates whether the most recent EDPCSR sample was associated with EL2.

If EL2 is not implemented, this bit is RES0.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

E3, bit [29]

Exception level 3 status sample. Indicates whether the most recent EDPCSR sample was associated with EL3 using AArch64.

If EDVIDSR.NS == 1 or the PE was in AArch32 state when EDPCSRlo (EDPCSR[31:0]) was read, this bit is 0.

If EL3 is not implemented, this bit is RES0.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

HV, bit [28]

EDPCSRhi (EDPCSR[63:32]) valid. Indicates whether bits [63:32] of the most recent EDPCSR sample might be nonzero:

HVMeaning
0b0

Bits[63:32] of the most recent EDPCSR sample are zero.

0b1

Bits[63:32] of the most recent EDPCSR sample might be nonzero.

An EDVIDSR.HV value of 1 does not mean that the value of EDPCSRhi is nonzero.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bits [27:8]

Reserved, RES0.

VMID, bits [7:0]

VMID sample. The VMID associated with the most recent EDPCSRlo (EDPCSR[31:0]) sample.

If EL2 is using AArch64 and the value of EDVIDSR.NS is 0 or the value of EDVIDSR.E2 is 1 this field is RES0.

If EL2 is not implemented, then this field is RES0.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

When ARMv8.1-VHE is implemented and EDSCR.SC2 == 0:
313029282726252423222120191817161514131211109876543210
NSE2E3HV000000000000VMID

This format applies in all Armv8.0 implementations.

NS, bit [31]

From Armv8.1:

Non-secure state sample. Indicates the Security state associated with the most recent EDPCSR sample.

If EL3 is not implemented, this bit indicates the Effective value of SCR.NS.

On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

E2, bit [30]

From Armv8.1:

Exception level 2 status sample. Indicates whether the most recent EDPCSR sample was associated with EL2.

If EL2 is not implemented, this bit is RES0.

On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

E3, bit [29]

From Armv8.1:

Exception level 3 status sample. Indicates whether the most recent EDPCSR sample was associated with EL3 using AArch64.

If EDVIDSR.NS == 1 or the PE was in AArch32 state when EDPCSRlo (EDPCSR[31:0]) was read, this bit is 0.

If EL3 is not implemented, this bit is RES0.

On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

HV, bit [28]

From Armv8.1:

EDPCSRhi (EDPCSR[63:32]) valid. Indicates whether bits [63:32] of the most recent EDPCSR sample might be nonzero:

HVMeaning
0b0

Bits[63:32] of the most recent EDPCSR sample are zero.

0b1

Bits[63:32] of the most recent EDPCSR sample might be nonzero.

An EDVIDSR.HV value of 1 does not mean that the value of EDPCSRhi is nonzero. An EDVIDSR.HV value of 0 is a hint that EDPCSRhi (EDPCSR[63:32]) does not need to be read.

On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [27:16]

Reserved, RES0.

VMID, bits [15:0]

From Armv8.1:

VMID sample. The VMID associated with the most recent EDPCSRlo (EDPCSR[31:0]) sample.

  • If EL2 is using AArch64 and the value of EDVIDSR.NS is 0 or the value of EDVIDSR.E2 is 1 this field is RES0.
  • If EL2 is not implemented, this field is RES0.
  • If EL2 is implemented and is using AArch64, the VMID is held in VTTBR_EL2.VMID.
  • If EL2 is implemented and is using AArch32, the VMID is held in VTTBR.VMID.
  • If 16-bit VMIDs are not supported, EDVIDSR.VMID[15:8] is RES0.
  • If 16-bit VMIDs are supported, but VTTBRx.VMID[15:8] are not used, EDVIDSR.VMID[15:8] is set to 0.

On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

When ARMv8.1-VHE is implemented and EDSCR.SC2 == 1:
313029282726252423222120191817161514131211109876543210
CONTEXTIDR_EL2

CONTEXTIDR_EL2, bits [31:0]

From Armv8.1:

Context ID.

  • If EL2 is using AArch64 and if the value of EDPCSR.NS is 0, the value of CONTEXTIDR_EL2 as associated with the most recent EDPCSR sample.
  • If the value of EDPCSR.NS is 0, then this field is set to an UNKNOWN value.
  • If neither of the above conditions are true, this field is set to an UNKNOWN value.

On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Accessing the EDVIDSR

IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile

EDVIDSR can be accessed through the external debug interface:

ComponentOffsetInstance
Debug0x0A8EDVIDSR

This interface is accessible as follows:

  • When IsCorePowered(), !DoubleLockStatus() and !OSLockStatus() access to this register is RO.
  • Otherwise access to this register returns an Error.


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