ERRCIDR1, Component Identification Register 1
The ERRCIDR1 characteristics are:
Provides discovery information for the component.
Implementation of this register is OPTIONAL.
This register is present only when RAS is implemented. Otherwise, direct accesses to ERRCIDR1 are RES0.
ERRCIDR1 is a 32-bit register.
The ERRCIDR1 bit assignments are:
CLASS, bits [7:4]
Generic peripheral with IMPLEMENTATION DEFINED register layout.
This field reads as 0xF.
Other values are defined by the CoreSight Architecture.
PRMBL_1, bits [3:0]
Component identification preamble, segment 1. This field reads as 0x0.
Accessing the ERRCIDR1
ERRCIDR1 can be accessed through the memory-mapped interfaces:
Access on this interface is RO.