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ERR<n>ADDR, Error Record Address Register, n = 0 - 65534

The ERR<n>ADDR characteristics are:

Purpose

If an error has an associated address, then this must be written to the address register when the error is recorded. It is IMPLEMENTATION DEFINED how the recorded addresses map to the software-visible physical addresses.

Software might have to reconstruct the actual physical addresses using the identity of the node and knowledge of the system.

Configuration

Some or all RW fields of this register have defined reset values.

This register is present only when RAS is implemented. Otherwise, direct accesses to ERR<n>ADDR are UNDEFINED.

The number of error records that are implemented is IMPLEMENTATION DEFINED.

If error record <n> is not implemented, ERR<n>ADDR is RES0.

ERR<q>FR describes the features implemented by the node that owns error record <n>. <q> is the index of the first error record owned by the same node as error record <n>. If the node owns a single record, then q = n.

Attributes

ERR<n>ADDR is a 64-bit register.

Field descriptions

The ERR<n>ADDR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
NSSIAIVA0000PADDR
PADDR
313029282726252423222120191817161514131211109876543210

NS, bit [63]

Non-secure attribute.

NSMeaning
0b0

The address is Secure.

0b1

The address is Non-secure.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

SI, bit [62]

Secure Incorrect.

Indicates whether the NS bit is valid.

SIMeaning
0b0

The NS bit is correct. That is, it matches the programmers' view of the Non-secure attribute for this recorded location.

0b1

The NS bit might not be correct, and might not match the programmers' view of the Non-secure attribute for the recorded location.

It is IMPLEMENTATION DEFINED whether this bit is read-only or read/write.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

AI, bit [61]

Address Incorrect.

Indicates whether the PADDR field is a valid physical address that is known to match the programmers' view of the physical address for the recorded location.

AIMeaning
0b0

The PADDR field is a valid physical address. That is, it matches the programmers' view of the physical address for the recorded location.

0b1

The PADDR field might not be a valid physical address, and might not match the programmers' view of the physical address for the recorded location.

It is IMPLEMENTATION DEFINED whether this bit is read-only or read/write.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

VA, bit [60]

Virtual Address.

Indicates whether the PADDR field is a virtual address.

VAMeaning
0b0

The PADDR field is not a virtual address.

0b1

The PADDR field is a virtual address.

No context information is provided for the virtual address. When this bit is set to 1, ERR<n>ADDR.{NS,SI,AI} must read as {0,1,1}.

Support for this bit is optional. If this bit is not implemented and the PADDR field is a virtual address, then ERR<n>ADDR.{NS,SI,AI} must read as {0,1,1}.

It is IMPLEMENTATION DEFINED whether this bit is read-only or read/write.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bits [59:56]

Reserved, RES0.

PADDR, bits [55:0]

Physical Address. Address of the recorded location.

If the physical address size implemented by this component is smaller than the size of this field, then high-order bits are unimplemented and either RES0 or have a fixed read-only IMPLEMENTATION DEFINED value.

Low-order address bits might also be unimplemented and RES0, for example, if the physical address is always aligned to the size of a protection granule.

The following resets apply:

  • This field is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing the ERR<n>ADDR

ERR<n>ADDR ignores writes if ERR<n>STATUS.AV is set to 1.

ERR<n>ADDR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0x018 + 64nERR<n>ADDR

Access on this interface is RW.



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