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ERR<n>MISC3, Error Record Miscellaneous Register 3, n = 0 - 65534

The ERR<n>MISC3 characteristics are:

Purpose

IMPLEMENTATION DEFINED error syndrome register. The miscellaneous syndrome registers can contain:

  • A Corrected error counter or counters.

  • Information to identify the FRU in which the error was detected, and might contain enough information to locate the error within that FRU.

  • Other state information not present in the corresponding status and address registers.

If the node <q> that owns error record <n> supports the RAS Timestamp Extension, then ERR<n>MISC3 contains the timestamp value for error record <n> when the error was detected. Otherwise the contents of ERR<n>MISC3 are IMPLEMENTATION DEFINED.

Configuration

External register ERR<n>MISC3 is architecturally mapped to AArch64 System register ERXMISC3_EL1 when ERRSELR_EL1.SEL == n.

External register ERR<n>MISC3 bits [31:0] are architecturally mapped to AArch32 System register ERXMISC6[31:0] when ERRSELR_EL1.SEL == n.

External register ERR<n>MISC3 bits [63:32] are architecturally mapped to AArch32 System register ERXMISC7[31:0] when ERRSELR_EL1.SEL == n.

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when ARMv8.4-RAS is implemented. Otherwise, direct accesses to ERR<n>MISC3 are RES0.

The number of error records that are implemented is IMPLEMENTATION DEFINED.

If error record <n> is not implemented, ERR<n>MISC3 is RES0.

ERR<q>FR describes the features implemented by the node that owns error record <n>. <q> is the index of the first error record owned by the same node as error record <n>. If the node owns a single record, then q = n.

Attributes

ERR<n>MISC3 is a 64-bit register.

Field descriptions

The ERR<n>MISC3 bit assignments are:

When ERR<q>FR.TS != 0b00:
6362616059585756555453525150494847464544434241403938373635343332
TS
TS

TS, bits [63:0]

Timestamp.

Timestamp value recorded when the error was detected. Valid only if ERR<n>STATUS.V == 1.

See ERR<n>FR.TS.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Access to this field is RO or RW.

When ERR<q>FR.TS == 0b00:
6362616059585756555453525150494847464544434241403938373635343332
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED
313029282726252423222120191817161514131211109876543210
313029282726252423222120191817161514131211109876543210

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

Accessing the ERR<n>MISC3

Arm recommends that a miscellaneous syndrome for multiple errors, such as a corrected error counter, is read/write.

When ERR<n>STATUS.MV is set to 1, the miscellaneous syndrome for the most recently recorded error should ignore writes.

ERR<n>MISC3 can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0x038 + 64nERR<n>MISC3

Access on this interface is RW.



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