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GICC_IIDR, CPU Interface Identification Register

The GICC_IIDR characteristics are:

Purpose

Provides information about the implementer and revision of the CPU interface.

Configuration

Attributes

GICC_IIDR is a 32-bit register.

Field descriptions

The GICC_IIDR bit assignments are:

313029282726252423222120191817161514131211109876543210
ProductIDArchitecture_versionRevisionImplementer

ProductID, bits [31:20]

An IMPLEMENTATION DEFINED product identifier.

Architecture_version, bits [19:16]

The version of the GIC architecture that is implemented.

Architecture_versionMeaning
0b0001

GICv1.

0b0010

GICv2.

0b0011

GICv3 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1.

0b0100

GICv4 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1.

Other values are reserved.

Revision, bits [15:12]

An IMPLEMENTATION DEFINED revision number for the CPU interface.

Implementer, bits [11:0]

Contains the JEP106 code of the company that implemented the CPU interface.

  • Bits [11:8] are the JEP106 continuation code of the implementer. For an Arm implementation, this field is 0x4.
  • Bit [7] is always 0.
  • Bits [6:0] are the JEP106 identity code of the implementer. For an Arm implementation, bits [7:0] are therefore 0x3B.

Accessing the GICC_IIDR

GICC_IIDR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
GIC CPU interface0x00FCGICC_IIDR

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0b0 access to this register is RO.
  • When IsAccessSecure() access to this register is RO.
  • When !IsAccessSecure() access to this register is RO.


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