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GICD_STATUSR, Error Reporting Status Register

The GICD_STATUSR characteristics are:

Purpose

Provides software with a mechanism to detect:

  • Accesses to reserved locations.
  • Writes to read-only locations.
  • Reads of write-only locations.

Configuration

If the GIC implementation supports two Security states this register is Banked to provide Secure and Non-secure copies.

Attributes

GICD_STATUSR is a 32-bit register.

Field descriptions

The GICD_STATUSR bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000000000WRODRWODWRDRRD

Bits [31:4]

Reserved, RES0.

WROD, bit [3]

Write to an RO location.

WRODMeaning
0b0

Normal operation.

0b1

A write to an RO location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

RWOD, bit [2]

Read of a WO location.

RWODMeaning
0b0

Normal operation.

0b1

A read of a WO location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

WRD, bit [1]

Write to a reserved location.

WRDMeaning
0b0

Normal operation.

0b1

A write to a reserved location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

RRD, bit [0]

Read of a reserved location.

RRDMeaning
0b0

Normal operation.

0b1

A read of a reserved location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

Accessing the GICD_STATUSR

This is an optional register. If the register is not implemented, the location is RAZ/WI.

GICD_STATUSR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
GIC Distributor0x0010GICD_STATUSR (S)

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0b0 access to this register is RW.
  • When IsAccessSecure() access to this register is RW.
ComponentOffsetInstance
GIC Distributor0x0010GICD_STATUSR (NS)

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0b0 access to this register is RW.
  • When !IsAccessSecure() access to this register is RW.


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