GICR_ISENABLER0, Interrupt Set-Enable Register 0
The GICR_ISENABLER0 characteristics are:
Enables forwarding of the corresponding SGI or PPI to the CPU interfaces.
Some or all RW fields of this register have defined reset values.
A copy of this register is provided for each Redistributor.
GICR_ISENABLER0 is a 32-bit register.
The GICR_ISENABLER0 bit assignments are:
|Set_enable_bit<x>, bit [x], for x = 0 to 31|
Set_enable_bit<x>, bit [x], for x = 0 to 31
For PPIs and SGIs, controls the forwarding of interrupt number x to the CPU interface. Reads and writes have the following behavior:
If read, indicates that forwarding of the corresponding interrupt is disabled.
If written, has no effect.
If read, indicates that forwarding of the corresponding interrupt is enabled.
If written, enables forwarding of the corresponding interrupt.
After a write of 1 to this bit, a subsequent read of this bit returns 1.
This field resets to 0.
Accessing the GICR_ISENABLER0
When affinity routing is not enabled for the Security state of an interrupt in GICR_ISENABLER0, the corresponding bit is RAZ/WI and equivalent functionality is provided by GICD_ISENABLER<n> with n=0.
This register only applies to SGIs (bits [15:0]) and PPIs (bits [31:16]). For SPIs, this functionality is provided by GICD_ISENABLER<n>.
When GICD_CTLR.DS == 0, bits corresponding to Secure SGIs and PPIs are RAZ/WI to Non-secure accesses.
GICR_ISENABLER0 can be accessed through the memory-mapped interfaces:
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 access to this register is RW.
- When IsAccessSecure() access to this register is RW.
- When !IsAccessSecure() access to this register is RW.