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GICR_PENDBASER, Redistributor LPI Pending Table Base Address Register

The GICR_PENDBASER characteristics are:

Purpose

Specifies the base address of the LPI Pending table, and the Shareability and Cacheability of accesses to the LPI Pending table.

Configuration

RW fields in this register reset to architecturally UNKNOWN values.

A copy of this register is provided for each Redistributor.

Attributes

GICR_PENDBASER is a 64-bit register.

Field descriptions

The GICR_PENDBASER bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
0PTZ000OuterCache0000Physical_Address
Physical_Address0000ShareabilityInnerCache0000000
313029282726252423222120191817161514131211109876543210

Bit [63]

Reserved, RES0.

PTZ, bit [62]

Pending Table Zero. Indicates to the Redistributor whether the LPI Pending table is zero when GICR_CTLR.EnableLPIs == 1.

This field is WO, and reads as 0.

PTZMeaning
0b0

The LPI Pending table is not zero, and contains live data.

0b1

The LPI Pending table is zero. Software must ensure the LPI Pending table is zero before this value is written.

Bits [61:59]

Reserved, RES0.

OuterCache, bits [58:56]

Indicates the Outer Cacheability attributes of accesses to the LPI Pending table. The possible values of this field are:

OuterCacheMeaning
0b000

Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability.

0b001

Normal Outer Non-cacheable.

0b010

Normal Outer Cacheable Read-allocate, Write-through.

0b011

Normal Outer Cacheable Read-allocate, Write-back.

0b100

Normal Outer Cacheable Write-allocate, Write-through.

0b101

Normal Outer Cacheable Write-allocate, Write-back.

0b110

Normal Outer Cacheable Read-allocate, Write-allocate, Write-through.

0b111

Normal Outer Cacheable Read-allocate, Write-allocate, Write-back.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

This field resets to an architecturally UNKNOWN value.

Bits [55:52]

Reserved, RES0.

Physical_Address, bits [51:16]

Bits [51:16] of the physical address containing the LPI Pending table.

In implementations supporting fewer than 52 bits of physical address, unimplemented upper bits are RES0.

This field resets to an architecturally UNKNOWN value.

Bits [15:12]

Reserved, RES0.

Shareability, bits [11:10]

Indicates the Shareability attributes of accesses to the LPI Pending table. The possible values of this field are:

ShareabilityMeaning
0b00

Non-shareable.

0b01

Inner Shareable.

0b10

Outer Shareable.

0b11

Reserved. Treated as 0b00.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

This field resets to an architecturally UNKNOWN value.

InnerCache, bits [9:7]

Indicates the Inner Cacheability attributes of accesses to the LPI Pending table. The possible values of this field are:

InnerCacheMeaning
0b000

Device-nGnRnE.

0b001

Normal Inner Non-cacheable.

0b010

Normal Inner Cacheable Read-allocate, Write-through.

0b011

Normal Inner Cacheable Read-allocate, Write-back.

0b100

Normal Inner Cacheable Write-allocate, Write-through.

0b101

Normal Inner Cacheable Write-allocate, Write-back.

0b110

Normal Inner Cacheable Read-allocate, Write-allocate, Write-through.

0b111

Normal Inner Cacheable Read-allocate, Write-allocate, Write-back.

This field resets to an architecturally UNKNOWN value.

Bits [6:0]

Reserved, RES0.

Accessing the GICR_PENDBASER

Having the GICR_PENDBASER OuterCache, Shareability or InnerCache fields programmed to different values on different Redistributors with GICR_CTLR.EnableLPIs == 1 in the system is UNPREDICTABLE.

Changing GICR_PENDBASER with GICR_CTLR.EnableLPIs == 1 is UNPREDICTABLE.

GICR_PENDBASER can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC RedistributorRD_base0x0078GICR_PENDBASER

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0b0 access to this register is RW.
  • When IsAccessSecure() access to this register is RW.
  • When !IsAccessSecure() access to this register is RW.


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