GICR_SYNCR, Redistributor Synchronize Register
The GICR_SYNCR characteristics are:
Indicates completion of physical Redistributor operations.
A copy of this register is provided for each Redistributor.
GICR_SYNCR is a 32-bit register.
The GICR_SYNCR bit assignments are:
Busy, bit 
Indicates completion of any Redistributor operations as follows:
No operations are in progress.
A write is in progress to one or more of the following registers:
Accessing the GICR_SYNCR
Optionally, when this register is accessed, an implementation might wait until all operations are complete before returning a value, in which case GICR_SYNCR.Busy is always 0.
This register is mandatory in an implementation that supports LPIs and does not include an ITS. The functionality is IMPLEMENTATION DEFINED in an implementation that does include an ITS.
GICR_SYNCR can be accessed through the memory-mapped interfaces:
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 access to this register is RO.
- When IsAccessSecure() access to this register is RO.
- When !IsAccessSecure() access to this register is RO.