GICV_IIDR, Virtual Machine CPU Interface Identification Register

The GICV_IIDR characteristics are:

Purpose

Provides information about the implementer and revision of the virtual CPU interface.

Configuration

This register is available in all configurations of the GIC. If the GIC implementation supports two Security states this register is Common.

Attributes

GICV_IIDR is a 32-bit register.

Field descriptions

The GICV_IIDR bit assignments are:

ProductID, bits [31:20]

An IMPLEMENTATION DEFINED product identifier.

Architecture_version, bits [19:16]

The version of the GIC architecture that is implemented.

Other values are reserved.

Revision, bits [15:12]

An IMPLEMENTATION DEFINED revision number for the CPU interface.

Implementer, bits [11:0]

Contains the JEP106 code of the company that implemented the CPU interface.

• Bits [11:8] are the JEP106 continuation code of the implementer. For an Arm implementation, this field is 0x4.
• Bit [7] is always 0.
• Bits [6:0] are the JEP106 identity code of the implementer. For an Arm implementation, bits [7:0] are therefore 0x3B.

Accessing the GICV_IIDR

GICV_IIDR can be accessed through the memory-mapped interfaces:

This interface is accessible as follows:

• When GICD_CTLR.DS == 0b0 access to this register is RO.
• When IsAccessSecure() access to this register is RO.
• When !IsAccessSecure() access to this register is RO.