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ATS1HW, Address Translate Stage 1 Hyp mode Write
The ATS1HW characteristics are:
Purpose
Performs stage 1 address translation as defined for PL2 and the Non-secure state, with permissions as if writing to the given virtual address.
Configuration
Attributes
ATS1HW is a 32-bit System instruction.
Field descriptions
The ATS1HW input value bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Input address for translation | |||||||||||||||||||||||||||||||
Bits [31:0]
Input address for translation. The resulting address can be read from the PAR.
This System instruction takes a VA as input. The resulting address is the PA that is the output address of the translation.
Executing the ATS1HW instruction
If this instruction is executed in a Secure privileged mode other than Monitor mode, then the behavior is CONSTRAINED UNPREDICTABLE, and one of the following behaviors must occur:
- The instruction is UNDEFINED.
- The instruction is treated as a NOP.
- The instruction executes as if it had been executed in Monitor mode.
Accesses to this instruction use the following encodings:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b100 | 0b0111 | 0b1000 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then
AArch32.TakeHypTrapException(0x03);
else
ATS1HW(R[t]);
elsif PSTATE.EL == EL2 then
ATS1HW(R[t]);
elsif PSTATE.EL == EL3 then
ATS1HW(R[t]);