TLBI ALLE2IS, TLB Invalidate All, EL2, Inner Shareable
The TLBI ALLE2IS characteristics are:
Purpose
If EL2 is implemented and enabled in the current Security state, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
-
The entry is a stage 1 translation table entry, from any level of the translation table walk.
-
If SCR_EL3.NS is 1 and the entry would be required to translate an address using the Non-secure EL2 or Non-secure EL2&0 translation regime.
-
If SCR_EL3.NS is 0 and the entry would be required to translate an address using the Secure EL2 or Secure EL2&0 translation regime.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.
Configuration
Attributes
TLBI ALLE2IS is a 64-bit System instruction.
Field descriptions
TLBI ALLE2IS ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
Executing the TLBI ALLE2IS instruction
Accesses to this instruction use the following encodings:
TLBI ALLE2IS{, <Xt>}
op0 | op1 | CRn | CRm | op2 | Rt |
---|---|---|---|---|---|
0b01 | 0b100 | 0b1000 | 0b0011 | 0b000 | 0b11111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then TLBI_ALLE2IS(); elsif PSTATE.EL == EL3 then if !EL2Enabled() then UNDEFINED; else TLBI_ALLE2IS();