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TLBI RVALE2, TLB Range Invalidate by VA, Last level, EL2

The TLBI RVALE2 characteristics are:

Purpose

When EL2 is implemented and enabled in the current Security state, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

  • The entry is a stage 1 translation table entry.

  • The entry would be used to translate the specified VA in the specified range determined by the formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2^(5*SCALE +1) * Translation_Granule_Size)] using the EL2 or EL2&0 translation regime.

  • If HCR_EL2.E2H == 0, the entry is from the final level of the translation table walk.

  • If HCR_EL2.E2H == 1, one of the following applies:

    • The entry is a global entry from the final level of translation table walk.

    • The entry is a non-global entry from the final level of the translation table walk and matches the specified ASID.

The invalidation applies to the PE that executes this System instruction.

The range of addresses invalidated is UNPREDICTABLE when:

  • For the 4K translation granule:

    • If TTL==01 and BaseADDR[29:12] is not equal to 000000000000000000.

    • If TTL==10 and BaseADDR[20:12] is not equal to 000000000.

  • For the 16K translation granule:

    • If TTL==10 and BaseADDR[24:14] is not equal to 00000000000.
  • For the 64K translation granule:

    • If TTL==01 and BaseADDR[41:16] is not equal to 00000000000000000000000000.

    • If TTL==10 and BaseADDR[28:16] is not equal to 0000000000000.

Configuration

This instruction is present only when ARMv8.4-TLBI is implemented. Otherwise, direct accesses to TLBI RVALE2 are UNDEFINED.

Attributes

TLBI RVALE2 is a 64-bit System instruction.

Field descriptions

The TLBI RVALE2 input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
ASIDTGSCALENUMTTLBaseADDR
BaseADDR
313029282726252423222120191817161514131211109876543210

ASID, bits [63:48]

When HCR_EL2.E2H == 1:

ASID value to match. Any TLB entries that match the ASID value and VA value will be affected by this System instruction.

Global TLB entries that match the VA value will be affected by this System instruction, regardless of the value of the ASID field.

If the implementation supports 16 bits of ASID, but only 8 bits are being used in the context being invalidated, the upper bits are RES0.


Otherwise:

Reserved, RES0.

TG, bits [47:46]

Translation granule size.

TGMeaning
0b00

Reserved.

0b01

4K translation granule.

0b10

16K translation granule.

0b11

64K translation granule.

The instruction takes a translation granule size for the translations that are being invalidated. If the translations used a different translation granule size than the one being specified, then the architecture does not require that the instruction invalidates any entries.

SCALE, bits [45:44]

The exponent element of the calculation that is used to produce the upper range.

NUM, bits [43:39]

The base element of the calculation that is used to produce the upper range.

TTL, bits [38:37]

TTL Level hint. The TTL hint is only guaranteed to invalidate entries in the range that match the level described by the TTL hint.

TTLMeaning
0b00

The entries in the range can be using any level for the translation table entries.

0b01

When using a 4KB or 64KB translation granule, all entries to invalidate are Level 1 translation table entries.

When using a 16KB translation granule, this value is reserved and hardware should treat this field as 0b00.

0b10

All entries to invalidate are Level 2 translation table entries.

0b11

All entries to invalidate are Level 3 translation table entries.

BaseADDR, bits [36:0]

The starting address for the range of the maintenance instruction.

When using a 4KB translation granule, this field is BaseADDR[48:12].

When using a 16KB translation granule, this field is BaseADDR[50:14].

When using a 64KB translation granule, this field is BaseADDR[52:16].

Executing the TLBI RVALE2 instruction

Accesses to this instruction use the following encodings:

TLBI RVALE2{, <Xt>}

op0op1CRnCRmop2
0b010b1000b10000b01100b101
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    TLBI_RVALE2(X[t]);
elsif PSTATE.EL == EL3 then
    if !EL2Enabled() then
        UNDEFINED;
    else
        TLBI_RVALE2(X[t]);
              


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