AMEVCNTR0<n>_EL0, Activity Monitors Event Counter Registers 0, n = 0 - 15
The AMEVCNTR0<n>_EL0 characteristics are:
Purpose
Provides access to the architected activity monitor event counters.
Configuration
AArch64 System register AMEVCNTR0<n>_EL0 bits [63:0] are architecturally mapped to AArch32 System register AMEVCNTR0<n>[63:0] .
AArch64 System register AMEVCNTR0<n>_EL0 bits [63:0] are architecturally mapped to External register AMEVCNTR0<n>[63:0] .
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMEVCNTR0<n>_EL0 are UNDEFINED.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
Attributes
AMEVCNTR0<n>_EL0 is a 64-bit register.
Field descriptions
The AMEVCNTR0<n>_EL0 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| ACNT | |||||||||||||||||||||||||||||||
| ACNT | |||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACNT, bits [63:0]
Architected activity monitor event counter n.
Value of architected activity monitor event counter n, where n is the number of this register and is a number from 0 to 15.
If the counter is enabled, writes to this register have UNPREDICTABLE results.
On a Cold reset, this field resets to 0.
Accessing the AMEVCNTR0<n>_EL0
If <n> is greater than or equal to the number of architected activity monitor event counters, reads and writes of AMEVCNTR0<n>_EL0 are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:
- Accesses to the register are UNDEFINED.
- Accesses to the register behave as RAZ/WI.
- Accesses to the register execute as a NOP.
AMCGCR_EL0.CG0NC identifies the number of architected activity monitor event counters.
Accesses to this register use the following encodings:
MRS <Xt>, AMEVCNTR0<n>_EL0
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b1101 | 0b010[n:3] | 0b[n:2:0] |
if PSTATE.EL == EL0 then
if !ELUsingAArch32(EL1) && AMUSERENR_EL0.EN == '0' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return AMEVCNTR0_EL0[UInt(CRm<0>:op2<2:0>)];
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return AMEVCNTR0_EL0[UInt(CRm<0>:op2<2:0>)];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return AMEVCNTR0_EL0[UInt(CRm<0>:op2<2:0>)];
elsif PSTATE.EL == EL3 then
return AMEVCNTR0_EL0[UInt(CRm<0>:op2<2:0>)];
MSR AMEVCNTR0<n>_EL0, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b1101 | 0b010[n:3] | 0b[n:2:0] |
if IsHighestEL(PSTATE.EL) then
AMEVCNTR0_EL0[UInt(CRm<0>:op2<2:0>)] = X[t];
else
UNDEFINED;