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PMSIDR_EL1, Sampling Profiling ID Register

The PMSIDR_EL1 characteristics are:

Purpose

Describes the Statistical Profiling implementation to software

Configuration

This register is present only when SPE is implemented. Otherwise, direct accesses to PMSIDR_EL1 are UNDEFINED.

This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.

Attributes

PMSIDR_EL1 is a 64-bit register.

Field descriptions

The PMSIDR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0CountSizeMaxSizeIntervalRES0ERndLDSArchInstFLFTFE
313029282726252423222120191817161514131211109876543210

Bits [63:20]

Reserved, RES0.

CountSize, bits [19:16]

Defines the size of the counters

CountSizeMeaning
0b0010

12-bit saturating counters

All other values are reserved. Reserved values might be defined in a future version of the architecture.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

MaxSize, bits [15:12]

Defines the largest size for a single record, rounded up to a power-of-two. If this is the same as the minimum alignment (PMBIDR_EL1.Align), then each record is exactly this size

MaxSizeMeaning
0b0100

16 bytes

0b0101

32 bytes

0b0110

64 bytes

0b0111

128 bytes

0b1000

256 bytes

0b1001

512 bytes

0b1010

1024 bytes

0b1011

2KB

All other values are reserved. Reserved values might be defined in a future version of the architecture.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Interval, bits [11:8]

Recommended minimum sampling interval. This provides guidance from the implementer to the smallest minimum sampling interval, N.

IntervalMeaning
0b0000

256

0b0010

512

0b0011

768

0b0100

1,024

0b0101

1,536

0b0110

2,048

0b0111

3,072

0b1000

4,096

All other values are reserved. Reserved values might be defined in a future version of the architecture.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [7:6]

Reserved, RES0.

ERnd, bit [5]

Defines how the random number generator is used in determining the interval between samples, when enabled by PMSIRR_EL1.RND.

ERndMeaning
0b0

The random number is added at the start of the interval, and the sample is taken and a new interval started when the combined interval expires.

0b1

The random number is added and the new interval started after the interval programmed in PMSIRR_EL1.INTERVAL expires, and the sample is taken when the random interval expires.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

LDS, bit [4]

Data source indicator for sampled load instructions

LDSMeaning
0b0

Loaded data source not implemented

0b1

Loaded data source implemented

On a Warm reset, this field resets to an architecturally UNKNOWN value.

ArchInst, bit [3]

Architectural instruction profiling

ArchInstMeaning
0b0

Micro-op sampling implemented

0b1

Architecture instruction sampling implemented

On a Warm reset, this field resets to an architecturally UNKNOWN value.

FL, bit [2]

Filtering by latency. This bit is RAO.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

FT, bit [1]

Filtering by operation type. This bit is RAO.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

FE, bit [0]

Filtering by events. This bit is RAO.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing the PMSIDR_EL1

Accesses to this register use the following encodings:

MRS <Xt>, PMSIDR_EL1

op0op1CRnCRmop2
0b110b0000b10010b10010b111
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPMS == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return PMSIDR_EL1;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return PMSIDR_EL1;
elsif PSTATE.EL == EL3 then
    return PMSIDR_EL1;
              


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