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TFSR_EL3, Tag Fail Status Register (EL3).
The TFSR_EL3 characteristics are:
Purpose
Holds accumulated Tag Check Fails occurring in EL3 which are not taken precisely.
Configuration
This register is present only when ARMv8.5-MemTag is implemented. Otherwise, direct accesses to TFSR_EL3 are UNDEFINED.
RW fields in this register reset to architecturally UNKNOWN values.
Attributes
TFSR_EL3 is a 64-bit register.
Field descriptions
The TFSR_EL3 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | TF0 | ||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:1]
Reserved, RES0.
TF0, bit [0]
Tag Check Fail. Asynchronously set to 1 when a Tag Check fail using a virtual address with bit<55>==0b0 occurs.
This field resets to an architecturally UNKNOWN value.
Accessing the TFSR_EL3
Accesses to this register use the following encodings:
MRS <Xt>, TFSR_EL3
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b110 | 0b0110 | 0b0110 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
UNDEFINED;
elsif PSTATE.EL == EL2 then
UNDEFINED;
elsif PSTATE.EL == EL3 then
return TFSR_EL3;
MSR TFSR_EL3, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b110 | 0b0110 | 0b0110 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
UNDEFINED;
elsif PSTATE.EL == EL2 then
UNDEFINED;
elsif PSTATE.EL == EL3 then
TFSR_EL3 = X[t];