AMCNTENCLR0, Activity Monitors Count Enable Clear Register 0
The AMCNTENCLR0 characteristics are:
Disable control bits for the architected s event counters, AMEVCNTR0<n>.
External register AMCNTENCLR0 bits [31:0] are architecturally mapped to AArch64 System register AMCNTENCLR0_EL0[31:0] .
External register AMCNTENCLR0 bits [31:0] are architecturally mapped to AArch32 System register AMCNTENCLR0[31:0] .
The power domain of AMCNTENCLR0 is IMPLEMENTATION DEFINED. Some or all RW fields of this register have defined reset values. These apply only on a reset of the reset domain in which the register is implemented. The register is not affected by a reset of any other reset domain.
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMCNTENCLR0 are RES0.
AMCNTENCLR0 is a 32-bit register.
The AMCNTENCLR0 bit assignments are:
|P<n>, bit [n]|
P<n>, bit [n], for n = 0 to 31
Activity monitor event counter disable bit for AMEVCNTR0<n>.
Bits [31:N] are RAZ/WI. N is the value in AMCGCR.CG0NC.
Possible values of each bit are:
When read, means that AMEVCNTR0<n> is disabled. When written, has no effect.
On a Cold reset, this field resets to 0.
Accessing the AMCNTENCLR0
AMCNTENCLR0 can be accessed through the memory-mapped interfaces:
Access on this interface is RO.