You copied the Doc URL to your clipboard.

EDWAR, External Debug Watchpoint Address Register

The EDWAR characteristics are:

Purpose

Returns the virtual data address being accessed when a Watchpoint Debug Event was triggered.

Configuration

EDWAR is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

Attributes

EDWAR is a 64-bit register.

Field descriptions

The EDWAR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Watchpoint address
Watchpoint address
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Watchpoint address. The data virtual address being accessed when a Watchpoint Debug Event was triggered and caused entry to Debug state. This address must be within a naturally-aligned block of memory of power-of-two size no larger than the DC ZVA block size.

The value of this register is UNKNOWN if the PE is in Non-debug state, or if Debug state was entered other than for a Watchpoint debug event.

The value of EDWAR[63:32] is UNKNOWN if Debug state was entered for a Watchpoint debug event taken from AArch32 state.

The EDWAR is subject to the same alignment rules as the reporting of a watchpointed address in the FAR. See 'Determining the memory location that caused a Watchpoint exception' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D2 (AArch64 Self-hosted Debug)

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing the EDWAR

EDWAR can be accessed through the external debug interface:

ComponentOffsetInstanceRange
Debug0x030EDWAR31:0

This interface is accessible as follows:

  • When IsCorePowered(), !DoubleLockStatus() and !OSLockStatus() access to this register is RO.
  • Otherwise access to this register returns an Error.
ComponentOffsetInstanceRange
Debug0x034EDWAR63:32

This interface is accessible as follows:

  • When IsCorePowered(), !DoubleLockStatus() and !OSLockStatus() access to this register is RO.
  • Otherwise access to this register returns an Error.


Was this page helpful? Yes No