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ERRFHICR2, Fault-Handling Interrupt Configuration Register 2

The ERRFHICR2 characteristics are:

Purpose

Interrupt configuration register.

Configuration

External register ERRFHICR2 bits [31:0] are architecturally mapped to External register ERRIRQCR1[63:32] .

Some or all RW fields of this register have defined reset values.

This register is present only when RAS is implemented. Otherwise, direct accesses to ERRFHICR2 are RES0.

Present only if interrupt configuration registers use the recommended format. Otherwise, this register is RES0.

Attributes

ERRFHICR2 is a 32-bit register.

Field descriptions

The ERRFHICR2 bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0IRQENNSMSISHMemAttr

Bits [31:8]

Reserved, RES0.

IRQEN, bit [7]

Message Signaled Interrupt enable.

Enables generation of message signaled interrupts.

IRQENMeaning
0b0

Message signaled interrupts are disabled.

0b1

Message signaled interrupts are enabled.

If the component does not support disabling message signaled interrupts, this bit is RES0.

The following resets apply:

  • On a Error recovery reset, this field resets to 0.

  • On a Cold reset, this field resets to 0.

NSMSI, bit [6]

Security attribute.

Defines the physical address space for message signaled interrupts.

NSMSIMeaning
0b0

Physical address space for message signaled interrupts is Secure.

0b1

Physical address space for message signaled interrupts is Non-secure.

If the component prohibits Non-secure writes and does not support configuring the Security attribute, then the Security attribute for message signaled interrupts is IMPLEMENTATION DEFINED.

If the component allows Non-secure writes, then the Security attribute used for message signaled interrupts is Non-secure.

This bit is RES0 if any of the following are true:

  • The component allows Non-secure writes.

  • The component does not support configuring the Security attribute.

On a Cold reset, this field resets to an IMPLEMENTATION DEFINED value.

SH, bits [5:4]

Shareability.

Defines the Shareability domain for message signaled interrupts.

SHMeaning
0b00

Message signaled interrupts are in the Not shared Shareability domain.

0b10

Message signaled interrupts are in the Outer Shareable Shareability domain.

0b11

Message signaled interrupts are in the Inner Shareable Shareability domain.

If the component does not support configuring the Shareability domain, this field is RES0, meaning the Shareability domain for message signaled interrupts is IMPLEMENTATION DEFINED.

The following resets apply:

  • On a Error recovery reset, this field resets to an architecturally UNKNOWN value.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

MemAttr, bits [3:0]

Memory type.

Defines the memory type for message signaled interrupts. The values which correspond to each memory type are:

MemAttrMeaning
0b0000

Device-nGnRnE.

0b0001

Device-nGnRE.

0b0010

Device-nGRE.

0b0011

Device-GRE.

0b0101

Outer Non-cacheable, Inner Non-cacheable.

0b0110

Outer Non-cacheable, Inner Write-Through Cacheable.

0b0111

Outer Non-cacheable, Inner Write-Back Cacheable.

0b1001

Outer Write-Through Cacheable, Inner Non-cacheable.

0b1010

Outer Write-Through Cacheable, Inner Write-Through Cacheable.

0b1011

Outer Write-Through Cacheable, Inner Write-Back Cacheable.

0b1101

Outer Write-Back Cacheable, Inner Non-cacheable.

0b1110

Outer Write-Back Cacheable, Inner Write-Through Cacheable.

0b1111

Outer Write-Back Cacheable, Inner Write-Back Cacheable.

If the component does not support configuring the memory type, this field is RES0, meaning the memory type used for message signaled interrupts is IMPLEMENTATION DEFINED.

Note

This is the same format as the VMSAv8-64 stage 2 memory region attributes.

The following resets apply:

  • On a Error recovery reset, this field resets to an architecturally UNKNOWN value.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing the ERRFHICR2

ERRFHICR2 can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0xE8CERRFHICR2

Access on this interface is RW.



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