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ERRIRQSR, Error Interrupt Status Register

The ERRIRQSR characteristics are:

Purpose

Interrupt status register.

Configuration

External register ERRIRQSR is architecturally mapped to External register ERRIRQCR15.

RW fields in this register reset to architecturally UNKNOWN values.

Present only if interrupt configuration registers use the recommended format. Otherwise, this register is RES0.

Attributes

ERRIRQSR is a 64-bit register.

Field descriptions

The ERRIRQSR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0CRIERRCRIERIERRERIFHIERRFHI
313029282726252423222120191817161514131211109876543210

Bits [63:6]

Reserved, RES0.

CRIERR, bit [5]

Critical error interrupt error.

CRIERRMeaning
0b0

Interrupt write has not returned an error since this bit was last cleared to 0.

0b1

Interrupt write has returned an error since this bit was last cleared to 0.

This bit is read/write-one-to-clear.

The following resets apply:

  • On a Error recovery reset, this field resets to an architecturally UNKNOWN value.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

CRI, bit [4]

Critical error interrupt write in progress.

CRIMeaning
0b0

Interrupt write not in progress.

0b1

Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

This bit is read-only.

Note

This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

ERIERR, bit [3]

Error recovery interrupt error.

ERIERRMeaning
0b0

Interrupt write has not returned an error since this bit was last cleared to 0.

0b1

Interrupt write has returned an error since this bit was last cleared to 0.

This bit read/write-one-to-clear.

The following resets apply:

  • On a Error recovery reset, this field resets to an architecturally UNKNOWN value.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

ERI, bit [2]

Error recovery interrupt write in progress.

ERIMeaning
0b0

Interrupt write not in progress.

0b1

Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

This bit is read-only.

Note

This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

FHIERR, bit [1]

Fault handling interrupt error.

FHIERRMeaning
0b0

Interrupt write has not returned an error since this bit was last cleared to 0.

0b1

Interrupt write has returned an error since this bit was last cleared to 0.

This bit read/write-one-to-clear.

The following resets apply:

  • On a Error recovery reset, this field resets to an architecturally UNKNOWN value.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

FHI, bit [0]

Fault handling interrupt write in progress.

FHIMeaning
0b0

Interrupt write not in progress.

0b1

Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

This bit is read-only.

Note

This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

Accessing the ERRIRQSR

ERRIRQSR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0xEF8ERRIRQSR

Access on this interface is RW.



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