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ERR<n>FR, Error Record Feature Register, n = 0 - 65534

The ERR<n>FR characteristics are:

Purpose

Defines whether <n> is the first record owned by a node. If <n> is the first record owned by the node, also defines which of the common architecturally-defined features are implemented by the node and, of the implemented features, which are software programmable.

Configuration

This register is present only when RAS is implemented. Otherwise, direct accesses to ERR<n>FR are RES0.

Present only if error record <n> is implemented. Otherwise, this register is RES0.

The number of error records that are implemented is IMPLEMENTATION DEFINED.

If <n> is the first error record owned by a node, then ERR<n>FR.ED != 0b00.

If <n> is not the first error record owned by a node, then ERR<n>FR.ED == 0b00.

Attributes

ERR<n>FR is a 64-bit register.

Field descriptions

The ERR<n>FR bit assignments are:

When ERR<n>FR.ED != 0b00:
6362616059585756555453525150494847464544434241403938373635343332
IMPLEMENTATION DEFINED
RES0TSCIINJCEODUIRPCECCFIUEFIUIIMPLEMENTATION DEFINEDED

IMPLEMENTATION DEFINED, bits [63:32]

IMPLEMENTATION DEFINED.

Reserved for identifying IMPLEMENTATION DEFINED controls.

This field reads as an IMPLEMENTATION DEFINED value.

Bits [31:26]

Reserved, RES0.

TS, bits [25:24]

From Armv8.4:

Timestamp Extension.

Indicates whether, for each error record <m> owned by this node, ERR<m>MISC3 is used as the timestamp register, and, if it is, the timebase used by the timestamp.

TSMeaning
0b00

The node does not support a timestamp register.

0b01

The node implements a timestamp register. The timestamp uses the same timebase as the system Generic Timer.

Note

For an error record which has an affinity to a PE, this is the same timer that is visible through CNTPCT_EL0 at the highest Exception level on that PE.

0b10

The node implements a timestamp register. The timebase for the timestamp is IMPLEMENTATION DEFINED.

All other values are reserved.


Otherwise:

Reserved, RES0.

CI, bits [23:22]

Critical error interrupt.

Indicates whether the critical error interrupt and associated controls are implemented.

CIMeaning
0b00

Does not support critical error interrupt.

0b01

Critical error interrupt is supported and is always enabled.

0b10

Critical error interrupt is supported and it can be enabled using associated controls.

All other values are reserved.

INJ, bits [21:20]

From Armv8.4:

Fault Injection Extension.

Indicates whether the RAS Common Fault Injection Model Extension is implemented.

INJMeaning
0b00

The node does not support the RAS Common Fault Injection Model Extension.

0b01

The node implements the RAS Common Fault Injection Model Extension. See ERR<n>PFGF for more information.

All other values are reserved.


Otherwise:

Reserved, RES0.

CEO, bits [19:18]

When ERR<n>FR.CEC != 0b00:

Corrected Error overwrite.

Indicates the behavior when a second Corrected error is detected after a first Corrected error has been recorded by an error record <m> owned by the node.

CEOMeaning
0b00

Counts Corrected errors if a counter is implemented. Keeps the previous error syndrome. If the counter overflows, or no counter is implemented, then ERR<m>STATUS.OF is set to 1.

0b01

Counts Corrected errors. If ERR<m>STATUS.OF == 1 before the Corrected error is counted, then keeps the previous syndrome. Otherwise, the previous syndrome is overwritten. If the counter overflows, then ERR<m>STATUS.OF is set to 1.

All other values are reserved.


Otherwise:

Reserved, RES0.

DUI, bits [17:16]

When ERR<n>FR.UI != 0b00:

Error recovery interrupt for deferred errors.

Indicates whether the node implements a control for enabling error recovery interrupts on deferred errors.

DUIMeaning
0b00

Does not support feature. ERR<n>CTLR.DUI is RES0.

0b10

Feature is controllable using ERR<n>CTLR.DUI.

0b11

Feature is controllable using ERR<n>CTLR.WDUI for writes and ERR<n>CTLR.RDUI for reads.

All other values are reserved.


Otherwise:

Reserved, RES0.

RP, bit [15]

When ERR<n>FR.CEC != 0b00:

Repeat counter.

Indicates whether the node implements a repeat Corrected error counter in ERR<m>MISC0 for each error record <m> owned by the node that implements a standard Corrected error counter.

RPMeaning
0b0

A single CE counter is implemented.

0b1

A first (repeat) counter and a second (other) counter are implemented. The repeat counter is the same size as the primary error counter.


Otherwise:

Reserved, RES0.

CEC, bits [14:12]

Corrected Error Counter.

Indicates whether the node implements standard Corrected error counter (CE counter) mechanisms in ERR<m>MISC0 for each error record <m> owned by the node that can record countable errors.

CECMeaning
0b000

Does not implement the standard Corrected error counter model.

0b010

Implements an 8-bit Corrected error counter in ERR<m>MISC0[39:32].

0b100

Implements a 16-bit Corrected error counter in ERR<m>MISC0[47:32].

All other values are reserved.

Note

Implementations might include other error counter models, or might include the standard model and not indicate this in ERR<n>FR.

CFI, bits [11:10]

When ERR<n>FR.FI != 0b00:

Fault handling interrupt for corrected errors.

Indicates whether the node implements a control for enabling fault handling interrupts on corrected errors.

CFIMeaning
0b00

Does not support feature. ERR<n>CTLR.CFI is RES0.

0b10

Feature is controllable using ERR<n>CTLR.CFI.

0b11

Feature is controllable using ERR<n>CTLR.WCFI for writes and ERR<n>CTLR.RCFI for reads.

All other values are reserved.


Otherwise:

Reserved, RES0.

UE, bits [9:8]

In-band uncorrected error reporting.

Indicates whether the node implements in-band uncorrected error reporting (External aborts), and, if so, whether the node implements controls for enabling and disabling the reporting.

UEMeaning
0b00

Does not support feature. ERR<n>CTLR.UE is RES0.

0b01

Feature always enabled. ERR<n>CTLR.UE is RES0.

0b10

Feature is controllable using ERR<n>CTLR.UE.

0b11

Feature is controllable using ERR<n>CTLR.WUE for writes and ERR<n>CTLR.RUE for reads.

FI, bits [7:6]

Fault handling interrupt.

Indicates whether the node implements a fault handling interrupt, and, if so, whether the node implements controls for enabling and disabling the interrupt.

FIMeaning
0b00

Does not support feature. ERR<n>CTLR.FI is RES0.

0b01

Feature always enabled. ERR<n>CTLR.FI is RES0.

0b10

Feature is controllable using ERR<n>CTLR.FI.

0b11

Feature is controllable using ERR<n>CTLR.WFI for writes and ERR<n>CTLR.RFI for reads.

UI, bits [5:4]

Error recovery interrupt for uncorrected errors.

Indicates whether the node implements an error recovery interrupt, and, if so, whether the node implements controls for enabling and disabling the interrupt.

UIMeaning
0b00

Does not support feature. ERR<n>CTLR.UI is RES0.

0b01

Feature always enabled. ERR<n>CTLR.UI is RES0.

0b10

Feature is controllable using ERR<n>CTLR.UI.

0b11

Feature is controllable using ERR<n>CTLR.WUI for writes and ERR<n>CTLR.RUI for reads.

IMPLEMENTATION DEFINED, bits [3:2]

IMPLEMENTATION DEFINED.

This field reads as an IMPLEMENTATION DEFINED value.

ED, bits [1:0]

Error reporting and logging.

Indicates whether <n> is the first record owned by the node, and, if it is, whether the node implements controls for enabling and disabling error reporting and logging.

EDMeaning
0b01

Feature always enabled. ERR<n>CTLR.ED is RES0.

0b10

Feature is controllable using ERR<n>CTLR.ED.

The value 0b11 is reserved.

When ERR<n>FR.ED == 0b00:
6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0ED
313029282726252423222120191817161514131211109876543210
313029282726252423222120191817161514131211109876543210

Bits [63:2]

Reserved, RES0.

ED, bits [1:0]

Error reporting and logging.

Indicates whether <n> is the first record owned by the node, and, if it is, whether the node implements controls for enabling and disabling error reporting and logging.

EDMeaning
0b00

Error record <n> is not the first record owned by the node.

Accessing the ERR<n>FR

ERR<n>FR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0x000 + 64nERR<n>FR

Access on this interface is RO.



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