ERR<n>MISC1, Error Record Miscellaneous Register 1, n = 0 - 65534
The ERR<n>MISC1 characteristics are:
IMPLEMENTATION DEFINED error syndrome register. The miscellaneous syndrome registers can contain:
A Corrected error counter or counters.
Information to identify the FRU in which the error was detected, and might contain enough information to locate the error within that FRU.
Other state information not present in the corresponding status and address registers.
This register is present only when RAS is implemented. Otherwise, direct accesses to ERR<n>MISC1 are UNDEFINED.
The number of error records that are implemented is IMPLEMENTATION DEFINED.
If error record <n> is not implemented, ERR<n>MISC1 is RES0.
ERR<q>FR describes the features implemented by the node that owns error record <n>. <q> is the index of the first error record owned by the same node as error record <n>. If the node owns a single record, then q = n.
ERR<n>MISC1 is a 64-bit register.
The ERR<n>MISC1 bit assignments are:
IMPLEMENTATION DEFINED, bits [63:0]
IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.
Accessing the ERR<n>MISC1
Arm recommends that a miscellaneous syndrome for multiple errors, such as a corrected error counter, is read/write.
When ERR<n>STATUS.MV is set to 1, the miscellaneous syndrome for the most recently recorded error should ignore writes.
ERR<n>MISC1 can be accessed through the memory-mapped interfaces:
|RAS||0x028 + 64n||ERR<n>MISC1|
Access on this interface is RW.