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GICC_ABPR, CPU Interface Aliased Binary Point Register

The GICC_ABPR characteristics are:


Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 1 interrupt preemption.


RW fields in this register reset to architecturally UNKNOWN values.

In systems that support two Security states:

  • This register is an alias of the Non-secure copy of GICC_BPR.
  • Non-secure accesses to this register return a shifted value of the binary point.
  • If ICC_CTLR_EL3.CBPR_EL1NS == 1, Secure accesses to this register access ICC_BPR0_EL1.


The reset value of this register is defined as (minimum GICC_BPR.Binary_Point + 1), resulting in a permitted range of 0x1-0x4.

Field descriptions

The GICC_ABPR bit assignments are:


Bits [31:3]

Reserved, RES0.

Binary_Point, bits [2:0]

Controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. The following list describes how this field determines the interrupt priority bits assigned to the group priority field:

  • Priority grouping for Group 1 interrupts when CBPR==0, for the processing of Group 1 interrupts in a GIC implementation that supports interrupt grouping, when GICC_CTLR.CBPR == 0.
  • Priority grouping for Group 0 interrupts, or Group 1 interrupts when CBPR==1, for all other cases.

This field resets to an architecturally UNKNOWN value.

Accessing the GICC_ABPR

This register is used only when System register access is not enabled. When System register access is enabled, the System registers ICC_BPR0_EL1 and ICC_BPR1_EL1 provide equivalent functionality.

GICC_ABPR can be accessed through the memory-mapped interfaces:

GIC CPU interface0x001CGICC_ABPR

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0b0 access to this register is RW.
  • When IsAccessSecure() access to this register is RW.
  • When !IsAccessSecure() access to this register is RW.