GICD_ISENABLER<n>E, Interrupt Set-Enable Registers, n = 0 - 31
The GICD_ISENABLER<n>E characteristics are:
Enables forwarding of the corresponding SPI in the extended SPI range to the CPU interfaces.
Some or all RW fields of this register have defined reset values.
This register is present only when GIC, >=3.1 is implemented. Otherwise, direct accesses to GICD_ISENABLER<n>E are RES0.
When GICD_TYPER.ESPI==0, these registers are RES0.
GICD_ISENABLER<n>E is a 32-bit register.
The GICD_ISENABLER<n>E bit assignments are:
|Set_enable_bit<x>, bit [x], for x = 0 to 31|
Set_enable_bit<x>, bit [x], for x = 0 to 31
For the extended SPI range, controls the forwarding of interrupt number x to the CPU interface. Reads and writes have the following behavior:
If read, indicates that forwarding of the corresponding interrupt is disabled.
If written, has no effect.
If read, indicates that forwarding of the corresponding interrupt is enabled.
If written, enables forwarding of the corresponding interrupt.
After a write of 1 to this bit, a subsequent read of this bit returns 1.
This field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
The corresponding GICD_ISENABLER<n>E number, n, is given by n = (m-4096) DIV 32.
The offset of the required GICD_ISENABLER<n>E is (0x1200 + (4*n)).
The bit number of the required group modifier bit in this register is (m-4096) MOD 32.
Accessing the GICD_ISENABLER<n>E
When affinity routing is not enabled for the Security state of an interrupt in GICD_ISENABLER<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
GICD_ISENABLER<n>E can be accessed through the memory-mapped interfaces:
|GIC Distributor||0x1200 + 4n||GICD_ISENABLER<n>E|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 access to this register is RW.
- When IsAccessSecure() access to this register is RW.
- When !IsAccessSecure() access to this register is RW.