GICV_EOIR, Virtual Machine End Of Interrupt Register
The GICV_EOIR characteristics are:
A write to this register performs a priority drop for the specified Group 0 virtual interrupt and, if GICV_CTLR.EOImode == 0, also deactivates the interrupt.
This register corresponds to the physical CPU interface register GICC_EOIR.
This register is available when the GIC implementation supports interrupt virtualization.
GICV_EOIR is a 32-bit register.
The GICV_EOIR bit assignments are:
INTID, bits [24:0]
The INTID of the signaled interrupt.
INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.
When affinity routing is not enabled:
- Bits [23:13] are RES0.
- For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0.
The behavior of this register depends on the setting of GICV_CTLR.EOImode:
|0b0||Both the priority drop and the deactivate interrupt effects occur|
|0b1||Only the priority drop effect occurs.|
A successful EOI request means that:
- The highest priority bit in GICH_APR<n> is cleared, causing the running priority to drop.
- If the appropriate GICV_CTLR.EOImode bit == 0, the interrupt is deactivated in the corresponding List register GICH_LR<n>. If GICH_LR<n>.HW == 1, indicating the INTID corresponds to a hardware interrupt, a deactivate request is also sent to the physical Distributor, identifying the physical INTID from the corresponding field in the List register. This effect is identical to a Non-secure write to GICC_DIR from the PE having that physical INTID. This means that if the corresponding physical interrupt is marked as Group 0, and GICD_CTLR.DS == 0, the deactivation request is ignored. See GICC_EOIR for more information.
Only Group 1 interrupts can target the hypervisor, and therefore only Group 1 interrupts are deactivated in the Distributor.
Accessing the GICV_EOIR
This register is used only when System register access is not enabled. When System register access is enabled:
- For AArch32 implementations, ICC_EOIR0 provides equivalent functionality.
- For AArch64 implementations, ICC_EOIR0_EL1 provides equivalent functionality.
This register is used for Group 0 interrupts only. GICV_AEOIR provides equivalent functionality for Group 1 interrupts.
When affinity routing is enabled, it is a programming error to use memory-mapped registers to access the GIC.
GICV_EOIR can be accessed through the memory-mapped interfaces:
|GIC Virtual CPU interface||0x0010||GICV_EOIR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 access to this register is WO.
- When IsAccessSecure() access to this register is WO.
- When !IsAccessSecure() access to this register is WO.