You copied the Doc URL to your clipboard.

MIDR_EL1, Main ID Register

The MIDR_EL1 characteristics are:

Purpose

Provides identification information for the PE, including an implementer code for the device and a device ID number.

Configuration

External register MIDR_EL1 bits [31:0] are architecturally mapped to AArch64 System register MIDR_EL1[31:0] .

External register MIDR_EL1 bits [31:0] are architecturally mapped to AArch32 System register MIDR[31:0] .

It is IMPLEMENTATION DEFINED whether MIDR_EL1 is implemented in the Core power domain or in the Debug power domain.

Attributes

MIDR_EL1 is a 32-bit register.

Field descriptions

The MIDR_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
ImplementerVariantArchitecturePartNumRevision

Implementer, bits [31:24]

The Implementer code. This field must hold an implementer code that has been assigned by Arm. Assigned codes include the following:

Hex representationImplementer
0x00Reserved for software use
0xC0Ampere Computing
0x41Arm Limited
0x42Broadcom Corporation
0x43Cavium Inc.
0x44Digital Equipment Corporation
0x49Infineon Technologies AG
0x4DMotorola or Freescale Semiconductor Inc.
0x4ENVIDIA Corporation
0x50Applied Micro Circuits Corporation
0x51Qualcomm Inc.
0x56Marvell International Ltd.
0x69Intel Corporation

Arm can assign codes that are not published in this manual. All values not assigned by Arm are reserved and must not be used.

Variant, bits [23:20]

An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product.

Architecture, bits [19:16]

The permitted values of this field are:

ArchitectureMeaning
0b0001

Armv4.

0b0010

Armv4T.

0b0011

Armv5 (obsolete).

0b0100

Armv5T.

0b0101

Armv5TE.

0b0110

Armv5TEJ.

0b0111

Armv6.

0b1111

Architectural features are individually identified in the ID_* registers, see ID registers in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile

All other values are reserved.

PartNum, bits [15:4]

An IMPLEMENTATION DEFINED primary part number for the device.

On processors implemented by Arm, if the top four bits of the primary part number are 0x0 or 0x7, the variant and architecture are encoded differently.

Revision, bits [3:0]

An IMPLEMENTATION DEFINED revision number for the device.

Accessing the MIDR_EL1

MIDR_EL1 can be accessed through the external debug interface:

ComponentOffsetInstance
Debug0xD00MIDR_EL1

This interface is accessible as follows:

  • When IsCorePowered() and !DoubleLockStatus() access to this register is RO.
  • Otherwise access to this register is IMPDEF.


Was this page helpful? Yes No