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MPAMF_ECR, MPAM Error Control Register

The MPAMF_ECR characteristics are:

Purpose

MPAMF_ECR is a 32-bit read-write register that controls MPAM error interrupts for this MSC.

Configuration

The power domain of MPAMF_ECR is IMPLEMENTATION DEFINED.

If a MSC cannot encounter any of the error conditions listed in section 15.1, both the MPAMF_ESR and MPAMF_ECR must be RAZ/WI.

Attributes

MPAMF_ECR is a 32-bit register.

Field descriptions

The MPAMF_ECR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0INTEN

Bits [31:1]

Reserved, RES0.

INTEN, bit [0]

Interrupt Enable.

INTENMeaning
0b0

MPAM error interrupts are not generated.

0b1

MPAM error interrupts are generated.

Accessing the MPAMF_ECR

This register is part of the MPAMF_BASE memory frame. In a system that supports Secure and Non-secure memory maps, the MPAMF_BASE frame must be accessible in both Secure and Non-secure memory address maps.

MPAMF_ECR must be accessible from the Non-secure and Secure address maps.

MPAMF_ECR must be banked for the Secure and Non-secure address maps. The Secure instance accesses the error interrupt controls used for Secure PARTIDs, and the Non-secure instance accesses the error interrupt controls used for Non-secure PARTIDs.

MPAMF_ECR can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
MPAM.anyMPAMF_BASE_s0x00F0MPAMF_ECR_s

Access on this interface is RW.

ComponentFrameOffsetInstance
MPAM.anyMPAMF_BASE_ns0x00F0MPAMF_ECR_ns

Access on this interface is RW.



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