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MPAMF_PRI_IDR, MPAM Priority Partitioning Identification Register

The MPAMF_PRI_IDR characteristics are:

Purpose

The MPAMF_PRI_IDR is a 32-bit read-only register that indicates which MPAM priority partitioning features are present on this MSC. This register is only present if MPAMF_IDR.HAS_PRI_PART == 1.

Configuration

The power domain of MPAMF_PRI_IDR is IMPLEMENTATION DEFINED.

This register is present only when MPAMF_IDR.HAS_PRI_PART == 1. Otherwise, direct accesses to MPAMF_PRI_IDR are IMPLEMENTATION DEFINED.

Attributes

MPAMF_PRI_IDR is a 32-bit register.

Field descriptions

The MPAMF_PRI_IDR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0DSPRI_WDRES0DSPRI_0_IS_LOWHAS_DSPRIRES0INTPRI_WDRES0INTPRI_0_IS_LOWHAS_INTPRI

Bits [31:26]

Reserved, RES0.

DSPRI_WD, bits [25:20]

Number of implemented bits in the downstream priority field (DSPRI) of MPAMCFG_PRI.

If HAS_DSPRI == 1, this field must contain a value from 1 to 32, inclusive.

If HAS_DSPRI == 0, this field must be 0.

Bits [19:18]

Reserved, RES0.

DSPRI_0_IS_LOW, bit [17]

Indicates whether 0 in MPAMCFG_PRI.DSPRI is the lowest or the highest priority.

DSPRI_0_IS_LOWMeaning
0b0

In the MPAMCFG_PRI.DSPRI field, a value of 0 means the highest priority.

0b1

In the MPAMCFG_PRI.DSPRI field, a value of 0 means the lowest priority.

HAS_DSPRI, bit [16]

Indicates that this MSC implements the DSPRI field in the MPAMCFG_PRI register.

HAS_DSPRIMeaning
0b0

This MSC supports priority partitioning, but does not implement a downstream priority (DSPRI) field in the MPAMCFG_PRI register.

0b1

This MSC supports downstream priority partitioning and implements the downstream priority (DSPRI) field in the MPAMCFG_PRI register.

Bits [15:10]

Reserved, RES0.

INTPRI_WD, bits [9:4]

Number of implemented bits in the internal priority field (INTPRI) in the MPAMCFG_PRI register.

If HAS_INTPRI == 1, this field must contain a value from 1 to 32, inclusive.

If HAS_INTPRI == 0, this field must be 0.

Bits [3:2]

Reserved, RES0.

INTPRI_0_IS_LOW, bit [1]

Indicates whether 0 in MPAMCFG_PRI.INTPRI is the lowest or the highest priority.

INTPRI_0_IS_LOWMeaning
0b0

In the MPAMCFG_PRI.INTPRI field, a value of 0 means the highest priority.

0b1

In the MPAMCFG_PRI.INTPRI field, a value of 0 means the lowest priority.

HAS_INTPRI, bit [0]

Indicates that this MSC implements the INTPRI field in the MPAMCFG_PRI register.

HAS_INTPRIMeaning
0b0

This MSC supports priority partitioning, but does not implement the internal priority (INTPRI) field in the MPAMCFG_PRI register.

0b1

This MSC supports internal priority partitioning and implements the internal priority (INTPRI) field in the MPAMCFG_PRI register.

Accessing the MPAMF_PRI_IDR

This register is part of the MPAMF_BASE memory frame. In a system that supports Secure and Non-secure memory maps, the MPAMF_BASE frame must be accessible in both Secure and Non-secure memory address maps.

MPAMF_PRI_IDR must be accessible from the Non-secure and Secure address maps.

MPAMF_PRI_IDR is permitted to be shared between the Secure and Non-secure address maps unless the register contents is different for Secure and Non-secure partitions, when the register must be banked.

MPAMF_PRI_IDR can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
MPAM.anyMPAMF_BASE_s0x0048MPAMF_PRI_IDR_s

Access on this interface is RO.

ComponentFrameOffsetInstance
MPAM.anyMPAMF_BASE_ns0x0048MPAMF_PRI_IDR_ns

Access on this interface is RO.



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