PMCEID2, Performance Monitors Common Event Identification register 2

The PMCEID2 characteristics are:

Purpose

Defines which common architectural events and common microarchitectural events are implemented, or counted, using PMU events in the range 0x4000 to 0x401F.

When the value of a bit in the register is 1 the corresponding common event is implemented and counted.

For more information about the common events and the use of the PMCEIDn registers see The section describing 'Event numbers and common events' in chapter D5 'The Performance Monitors Extension' of the Arm Architecture Reference Manual, for Armv8-A architecture profile.

Configuration

External register PMCEID2 bits [31:0] are architecturally mapped to AArch64 System register PMCEID0_EL0[63:32] .

External register PMCEID2 bits [63:32] are architecturally mapped to AArch32 System register PMCEID2[31:0] .

PMCEID2 is in the Core power domain.

This register is present only from Armv8.1. Otherwise, direct accesses to PMCEID2 are RES0.

Attributes

PMCEID2 is a 32-bit register.

Field descriptions

The PMCEID2 bit assignments are:

IDhi<n>, bit [n], for n = 0 to 31

From Armv8.1:

IDhi[n] corresponds to common event (0x4000 + n).

For each bit:

A bit that corresponds to a reserved event number is reserved. The value might be used in a future revision of the architecture to identify an additional common event.

Otherwise:

Reserved, RES0.

Accessing the PMCEID2

PMCEID2 can be accessed through the external debug interface:

This interface is accessible as follows:

• When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and AllowExternalPMUAccess() access to this register is RO.
• Otherwise access to this register returns an Error.