TLBIMVALHIS, TLB Invalidate by VA, Last level, Hyp mode, Inner Shareable
The TLBIMVALHIS characteristics are:
Purpose
If EL2 is implemented, invalidate all cached copies of translation table entries from TLBs that are from the final level of the translation table walk that would be required for the Non-secure EL2 translation regime and used to translate the specified address.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.
Configuration
This System instruction is not implemented in architecture versions before Armv8.
Attributes
TLBIMVALHIS is a 32-bit System instruction.
Field descriptions
The TLBIMVALHIS input value bit assignments are:
VA, bits [31:12]
Virtual address to match. Any TLB entries that match the ASID value and VA value will be affected by this System instruction.
Bits [11:0]
Reserved, RES0.
Executing the TLBIMVALHIS instruction
If this instruction is executed in a Secure privileged mode other than Monitor mode, then the behavior is CONSTRAINED UNPREDICTABLE, and one of the following behaviors must occur:
- The instruction is UNDEFINED.
- The instruction is treated as a NOP.
- The instruction executes as if it had been executed in Monitor mode.
Accesses to this instruction use the following encodings:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b100 | 0b1000 | 0b0011 | 0b101 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T8 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T8 == '1' then
AArch32.TakeHypTrapException(0x03);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
TLBIMVALHIS(R[t]);
elsif PSTATE.EL == EL3 then
if !HaveEL(EL2) then
UNDEFINED;
else
TLBIMVALHIS(R[t]);