NMRR, Normal Memory Remap Register
The NMRR characteristics are:
Purpose
Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in the PRRR.
Used in conjunction with the PRRR.
Configuration
AArch32 System register NMRR bits [31:0] are architecturally mapped to AArch64 System register MAIR_EL1[63:32] .
MAIR1 and NMRR are the same register, with a different view depending on the value of TTBCR.EAE:
- When it is set to 0, the register is as described in NMRR.
- When it is set to 1, the register is as described in MAIR1.
RW fields in this register reset to architecturally UNKNOWN values.
Attributes
NMRR is a 32-bit register.
Field descriptions
The NMRR bit assignments are:
When TTBCR.EAE == 0:
OR<n>, bits [2n+17:2n+16], for n = 0 to 7
Outer Cacheable property mapping for memory attributes n, if the region is mapped as Normal memory by the PRRR.TR<n> entry. n is the value of the TEX[0], C, and B bits concatenated. The possible values of this field are:
| OR<n> | Meaning |
|---|---|
| 0b00 |
Region is Non-cacheable. |
| 0b01 |
Region is Write-Back, Write-Allocate. |
| 0b10 |
Region is Write-Through, no Write-Allocate. |
| 0b11 |
Region is Write-Back, no Write-Allocate. |
The meaning of the field with n = 6 is IMPLEMENTATION DEFINED and might differ from the meaning given here. This is because the meaning of the attribute combination {TEX[0] = 1, C = 1, B = 0} is IMPLEMENTATION DEFINED.
This field resets to an architecturally UNKNOWN value.
IR<n>, bits [2n+1:2n], for n = 0 to 7
Inner Cacheable property mapping for memory attributes n, if the region is mapped as Normal memory by the PRRR.TR<n> entry. n is the value of the TEX[0], C, and B bits concatenated. The possible values of this field are:
| IR<n> | Meaning |
|---|---|
| 0b00 |
Region is Non-cacheable. |
| 0b01 |
Region is Write-Back, Write-Allocate. |
| 0b10 |
Region is Write-Through, no Write-Allocate. |
| 0b11 |
Region is Write-Back, no Write-Allocate. |
The meaning of the field with n = 6 is IMPLEMENTATION DEFINED and might differ from the meaning given here. This is because the meaning of the attribute combination {TEX[0] = 1, C = 1, B = 0} is IMPLEMENTATION DEFINED.
This field resets to an architecturally UNKNOWN value.
Accessing the NMRR
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1010 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T10 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TRVM == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) then
if SCR.NS == '0' then
return NMRR_S;
else
return NMRR_NS;
else
return NMRR;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && ELUsingAArch32(EL3) then
return NMRR_NS;
else
return NMRR;
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' then
return NMRR_S;
else
return NMRR_NS;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1010 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T10 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.NS == '0' && CP15SDISABLE == HIGH then
UNDEFINED;
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.NS == '0' && CP15SDISABLE2 == HIGH then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TVM == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) then
if SCR.NS == '0' then
NMRR_S = R[t];
else
NMRR_NS = R[t];
else
NMRR = R[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && ELUsingAArch32(EL3) then
NMRR_NS = R[t];
else
NMRR = R[t];
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' && CP15SDISABLE == HIGH then
UNDEFINED;
elsif SCR.NS == '0' && CP15SDISABLE2 == HIGH then
UNDEFINED;
else
if SCR.NS == '0' then
NMRR_S = R[t];
else
NMRR_NS = R[t];