AT S1E1RP, Address Translate Stage 1 EL1 Read PAN
The AT S1E1RP characteristics are:
Purpose
Performs a stage 1 address translation, where the value of PSTATE.PAN determines if a read from a location will generate a permission fault for a privileged access, using the following translation regime:
- When EL2 is implemented and enabled in the Security state described by the current value of SCR_EL3.NS:
- Otherwise, the EL1&0 translation regime, accessed from EL1.
Configuration
This instruction is present only when ARMv8.2-ATS1E1 is implemented. Otherwise, direct accesses to AT S1E1RP are UNDEFINED.
Attributes
AT S1E1RP is a 64-bit System instruction.
Field descriptions
The AT S1E1RP input value bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Input address for translation | |||||||||||||||||||||||||||||||
Input address for translation | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:0]
Input address for translation. The resulting address can be read from the PAR_EL1.
If the address translation instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then VA[63:32] is RES0.
Executing the AT S1E1RP instruction
Accesses to this instruction use the following encodings:
AT S1E1RP, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b000 | 0b0111 | 0b1001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.AT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AT_S1E1RP(X[t]); elsif PSTATE.EL == EL2 then AT_S1E1RP(X[t]); elsif PSTATE.EL == EL3 then AT_S1E1RP(X[t]);