DC IGDSW, Data, Allocation Tag or unified Cache line Invalidate of Data and Allocation Tags by Set/Way
The DC IGDSW characteristics are:
Invalidate data and Allocation Tags in data cache by set/way.
This instruction is present only when ARMv8.5-MemTag is implemented and ID_AA64PFR1_EL1.MTE != 0b0001. Otherwise, direct accesses to DC IGDSW are UNDEFINED.
DC IGDSW is a 64-bit System instruction.
The DC IGDSW input value bit assignments are:
SetWay, bits [31:4]
Contains two fields:
- Way, bits[31:32-A], the number of the way to operate on.
- Set, bits[B-1:L], the number of the set to operate on.
Bits[L-1:4] are RES0.
A = Log2(ASSOCIATIVITY), L = Log2(LINELEN), B = (L + S), S = Log2(NSETS).
ASSOCIATIVITY, LINELEN (line length, in bytes), and NSETS (number of sets) have their usual meanings and are the values for the cache level being operated on. The values of A and S are rounded up to the next integer.
Level, bits [3:1]
Cache level to operate on, minus 1. For example, this field is 0 for operations on L1 cache, or 1 for operations on L2 cache.
Executing the DC IGDSW instruction
If this instruction is executed with a set, way or level argument that is larger than the value supported by the implementation then the behavior is CONSTRAINED UNPREDICTABLE and one of the following occurs:
- The instruction is UNDEFINED.
- The instruction performs cache maintenance on one of:
- No cache lines.
- A single arbitrary cache line.
- Multiple arbitrary cache lines.
Accesses to this instruction use the following encodings:
DC IGDSW, <Xt>
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TSW == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.SWIO == '1' then DC_CIGDSW(X[t]); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<DC,VM> != '00' then DC_CIGDSW(X[t]); else DC_IGDSW(X[t]); elsif PSTATE.EL == EL2 then DC_IGDSW(X[t]); elsif PSTATE.EL == EL3 then DC_IGDSW(X[t]);