You copied the Doc URL to your clipboard.

TLBI VAE3OS, TLB Invalidate by VA, EL3, Outer Shareable

The TLBI VAE3OS characteristics are:

Purpose

If EL3 is implemented, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

  • The entry is a stage 1 translation table entry, from any level of the translation table walk.

  • The entry would be used to translate the specified VA using the EL3 translation regime.

The invalidation applies to all PEs in the same Outer Shareable shareability domain as the PE that executes this System instruction.

Configuration

This instruction is present only when ARMv8.4-TLBI is implemented. Otherwise, direct accesses to TLBI VAE3OS are UNDEFINED.

Attributes

TLBI VAE3OS is a 64-bit System instruction.

Field descriptions

The TLBI VAE3OS input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0TTLVA[55:12]
VA[55:12]
313029282726252423222120191817161514131211109876543210

Bits [63:48]

Reserved, RES0.

TTL, bits [47:44]

When ARMv8.4-TTL is implemented:

Translation Table Level. Indicates the level of the page table walk that holds the leaf entry for the address being invalidated.

TTLMeaning
0b00xx

No information supplied as to the translation table level. Hardware must assume that the entry can be from any level. In this case, TTL<1:0> is RES0.

0b01xx

The entry comes from a 4KB translation granule. The level of walk for the leaf level 0bxx is encoded as:

0b00 : Reserved. Treat as if TTL<3:2> is 0b00.

0b01 : Level 1.

0b10 : Level 2.

0b11 : Level 3.

0b10xx

The entry comes from a 16KB translation granule. The level of walk for the leaf level 0bxx is encoded as:

0b00 : Reserved. Treat as if TTL<3:2> is 0b00.

0b01 : Reserved. Treat as if TTL<3:2> is 0b00.

0b10 : Level 2.

0b11 : Level 3.

0b11xx

The entry comes from a 64KB translation granule. The level of walk for the leaf level 0bxx is encoded as:

0b00 : Reserved. Treat as if TTL<3:2> is 0b00.

0b01 : Level 1.

0b10 : Level 2.

0b11 : Level 3.

If an incorrect value of the TTL field is specified for the entry being invalidated by the instructio, then no entries are required by the architecture to be invalidated from the TLB.


Otherwise:

Reserved, RES0.

VA[55:12], bits [43:0]

Bits[55:12] of the virtual address to match. Any appropriate TLB entries that match the ASID value (if appropriate) and VA will be affected by this System instruction.

If the TLB maintenance instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then the software must treat bits[55:32] as RES0.

The treatment of the low-order bits of this field depends on the translation granule size, as follows:

  • Where a 4KB translation granule is being used, all bits are valid and used for the invalidation.

  • Where a 16KB translation granule is being used, bits [1:0] of this field are RES0 and ignored when the instruction is executed, because VA[13:12] have no effect on the operation of the instruction.

  • Where a 64KB translation granule is being used, bits [3:0] of this field are RES0 and ignored when the instruction is executed, because VA[15:12] have no effect on the operation of the instruction.

Executing the TLBI VAE3OS instruction

Accesses to this instruction use the following encodings:

TLBI VAE3OS{, <Xt>}

op0op1CRnCRmop2
0b010b1100b10000b00010b001
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    UNDEFINED;
elsif PSTATE.EL == EL2 then
    UNDEFINED;
elsif PSTATE.EL == EL3 then
    TLBI_VAE3OS(X[t]);
              


Was this page helpful? Yes No