ERXSTATUS_EL1, Selected Error Record Primary Status Register
The ERXSTATUS_EL1 characteristics are:
Purpose
Accesses ERR<n>STATUS for the error record selected by ERRSELR_EL1.SEL.
Configuration
AArch64 System register ERXSTATUS_EL1 bits [31:0] are architecturally mapped to AArch32 System register ERXSTATUS[31:0] .
This register is present only when RAS is implemented. Otherwise, direct accesses to ERXSTATUS_EL1 are UNDEFINED.
For IMPLEMENTATION DEFINED fields in this register, writing zero must always be supported to return the error record to an initial state.
In particular, if any IMPLEMENTATION DEFINED syndrome fields might generate a Fault Handling or Error Recovery Interrupt request, writing zero is sufficient to deactivate the Interrupt request.
Fields that are read-only, non-zero and ignore writes are compliant with this requirement.
Arm recommends that any IMPLEMENTATION DEFINED syndrome fields that can generate a Fault Handling, Error Recovery, Critical, or IMPLEMENTATION DEFINED, interrupt request are disabled at Cold reset and are enabled by software writing an IMPLEMENTATION DEFINED non-zero value to an IMPLEMENTATION DEFINED field in ERR<q>CTRL, where q is the index of the first error record owned by the same node as error record n. If the node owns a single record then q = n.
Attributes
ERXSTATUS_EL1 is a 64-bit register.
Field descriptions
The ERXSTATUS_EL1 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| ERR<n>STATUS | |||||||||||||||||||||||||||||||
| ERR<n>STATUS | |||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:0]
ERXSTATUS_EL1 accesses ERR<n>STATUS, where n is the value in ERRSELR_EL1.SEL.
Accessing the ERXSTATUS_EL1
If ERRIDR_EL1.NUM == 0 or ERRSELR_EL1.SEL is set to a value greater than or equal to ERRIDR_EL1.NUM, then one of the following occurs:
-
An UNKNOWN record is selected.
-
ERXSTATUS_EL1 is RAZ/WI.
-
Direct reads and writes of ERXSTATUS_EL1 are NOPs.
-
Direct reads and writes of ERXSTATUS_EL1 are UNDEFINED.
Accesses to this register use the following encodings:
MRS <Xt>, ERXSTATUS_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0101 | 0b0100 | 0b010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TERR == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TERR == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return ERXSTATUS_EL1;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TERR == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return ERXSTATUS_EL1;
elsif PSTATE.EL == EL3 then
return ERXSTATUS_EL1;
MSR ERXSTATUS_EL1, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0101 | 0b0100 | 0b010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TERR == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TERR == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
ERXSTATUS_EL1 = X[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TERR == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
ERXSTATUS_EL1 = X[t];
elsif PSTATE.EL == EL3 then
ERXSTATUS_EL1 = X[t];