ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1

The ID_AA64PFR1_EL1 characteristics are:

Purpose

Reserved for future expansion of information about implemented PE features in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

Configuration

Attributes

ID_AA64PFR1_EL1 is a 64-bit register.

Field descriptions

The ID_AA64PFR1_EL1 bit assignments are:

Bits [63:16]

Reserved, RES0.

RAS_frac, bits [15:12]

When ARMv8.4-RAS is implemented:

RAS Extension fractional field.

All other values are reserved.

This field is valid only if ID_AA64PFR0_EL1.RAS == 0b0001.

Otherwise:

Reserved, RES0.

MTE, bits [11:8]

When ARMv8.5-MemTag is implemented:

Support for the Tagged Memory Extension.

When only Memory Tagging Extension Instructions accessible at EL0 are implemented:

• All register fields added to existing System Registers as part of the extension are RES0 and treated as 0.

• The following System Registers are Unallocated:

  • GMID_EL1, GCR_EL1, RGSR_EL1, TFSRE0_EL1, and TFSR_ELx.

• The following System instructions are Unallocated:

  • DC CGSW, DC CIGSW, DC IGSW, DC CGDSW, DC CIGDSW, DC IGDSW, DC IGVAC, and DC IGDVAC.

• The following instructions are Unallocated:

  • LDGM, STGM, and STZGM.

All other values are reserved.

Otherwise:

Reserved, RES0.

SSBS, bits [7:4]

From Armv8.5:

Speculative Store Bypassing controls in AArch64 state. Defined values are:

All other values are reserved.

Otherwise:

Reserved, RES0.

BT, bits [3:0]

From Armv8.5:

Branch Target Identification mechanism support in AArch64 state. Defined values are:

All other values are reserved.

ARMv8.5-BTI implements the functionality identified by the value 0b0001.

From Armv8.5, the only permitted value is 0b0001.

Otherwise:

Reserved, RES0.

if PSTATE.EL == EL0 then
    if IsFeatureImplemented("ARMv8.4-IDST") then
        if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        return ID_AA64PFR1_EL1;
elsif PSTATE.EL == EL2 then
    return ID_AA64PFR1_EL1;
elsif PSTATE.EL == EL3 then
    return ID_AA64PFR1_EL1;