ID_AA64ZFR0_EL1, SVE Feature ID register 0
The ID_AA64ZFR0_EL1 characteristics are:
Purpose
Provides additional information about the implemented features of the AArch64 Scalable Vector Extension, when the ID_AA64PFR0_EL1.SVE field is not zero.
For general information about the interpretation of the ID registers see Principles of the ID scheme for fields in ID registers
Configuration
This register is present only when SVE is implemented. Otherwise, direct accesses to ID_AA64ZFR0_EL1 are RAZ.
Attributes
ID_AA64ZFR0_EL1 is a 64-bit register.
Field descriptions
The ID_AA64ZFR0_EL1 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | SVEver | ||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:4]
Reserved, RES0.
SVEver, bits [3:0]
Scalable Vector Extension instruction set version. The defined values of this field are:
| SVEver | Meaning |
|---|---|
| 0b0000 |
SVE instructions are implemented. |
All other values are reserved. This field is only valid if the ID_AA64PFR0_EL1.SVE field is not zero.
Accessing the ID_AA64ZFR0_EL1
Accesses to this register use the following encodings:
MRS <Xt>, ID_AA64ZFR0_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0100 | 0b100 |
if PSTATE.EL == EL0 then
if IsFeatureImplemented("ARMv8.4-IDST") then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
return ID_AA64ZFR0_EL1;
elsif PSTATE.EL == EL2 then
return ID_AA64ZFR0_EL1;
elsif PSTATE.EL == EL3 then
return ID_AA64ZFR0_EL1;