OSLSR_EL1, OS Lock Status Register
The OSLSR_EL1 characteristics are:
Purpose
Provides the status of the OS Lock.
Configuration
AArch64 System register OSLSR_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGOSLSR[31:0] .
This register is in the Cold reset domain. Some or all RW fields of this register have defined reset values. On a Cold reset these apply only if the PE resets into an Exception level that is using AArch64. Otherwise, on a Cold reset RW fields in this register reset to architecturally UNKNOWN values. The register is not affected by a Warm reset.
Attributes
OSLSR_EL1 is a 64-bit register.
Field descriptions
The OSLSR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | OSLM[1] | nTT | OSLK | OSLM[0] | |||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:4]
Reserved, RES0.
OSLM[1], bit [3]
This field is bit[1] of OSLM[1:0].
OS lock model implemented. Identifies the form of OS save and restore mechanism implemented.
OSLM | Meaning |
---|---|
0b00 |
OS Lock not implemented. |
0b10 |
OS Lock implemented. |
All other values are reserved. In an Armv8 implementation the value 0b00 is not permitted.
The OSLM field is split as follows:
- OSLM[1] is OSLSR_EL1[3].
- OSLM[0] is OSLSR_EL1[0].
nTT, bit [2]
Not 32-bit access. This bit is always RAZ. It indicates that a 32-bit access is needed to write the key to the OS Lock Access Register.
OSLK, bit [1]
OS Lock Status.
OSLK | Meaning |
---|---|
0b0 |
OS Lock unlocked. |
0b1 |
OS Lock locked. |
The OS Lock is locked and unlocked by writing to the OS Lock Access Register.
On a Cold reset, this field resets to 1.
OSLM[0], bit [0]
This field is bit[0] of OSLM[1:0].
See OSLM[1] for the field description.
Accessing the OSLSR_EL1
Accesses to this register use the following encodings:
MRS <Xt>, OSLSR_EL1
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b000 | 0b0001 | 0b0001 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDOSA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDOSA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return OSLSR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDOSA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return OSLSR_EL1; elsif PSTATE.EL == EL3 then return OSLSR_EL1;