TTBR0_EL2, Translation Table Base Register 0 (EL2)
The TTBR0_EL2 characteristics are:
Purpose
When HCR_EL2.E2H is 0, holds the base address of the translation table for the initial lookup for stage 1 of an address translation in the EL2 translation regime, and other information for this translation regime.
When HCR_EL2.E2H is 1, holds the base address of the translation table for the initial lookup for stage 1 of the translation of an address from the lower VA range in the EL2&0 translation regime, and other information for this translation regime.
Configuration
AArch64 System register TTBR0_EL2 bits [47:1] are architecturally mapped to AArch32 System register HTTBR[47:1] .
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
RW fields in this register reset to architecturally UNKNOWN values.
Attributes
TTBR0_EL2 is a 64bit register.
Field descriptions
The TTBR0_EL2 bit assignments are:
63  62  61  60  59  58  57  56  55  54  53  52  51  50  49  48  47  46  45  44  43  42  41  40  39  38  37  36  35  34  33  32 
ASID  BADDR  
BADDR  CnP  
31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0 
ASID, bits [63:48]
When ARMv8.1VHE is implemented:
When ARMv8.1VHE is implemented:
When HCR_EL2.E2H is 0, this field is RES0.
When HCR_EL2.E2H is 1, it holds an ASID for the translation table base address. The TCR_EL2.A1 field selects either TTBR0_EL2.ASID or TTBR1_EL2.ASID.
If the implementation has only 8 bits of ASID, then the upper 8 bits of this field are RES0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
BADDR, bits [47:1]
Translation table base address, A[47:x] or A[51:x], bits[47:1].
 Translation table base addresses of 52 bits, A[51:x], are supported only in an implementation that includes ARMv8.2LPA and is using the 64KB translation granule.
 A translation table must be aligned to the size of the table, except that when using a translation table base address larger than 48 bits the minimum alignment of a table containing fewer than eight entries is 64 bytes.
In an implementation that includes ARMv8.2LPA, if the value of TCR_EL2.{I}PS is 0b110, then:
 Register bits[47:z] hold bits[47:z] of the stage 1 translation table base address, where z is determined as follows:
 If x >= 6 then z=x.
 Otherwise, z=6.
 Register bits[5:2] hold bits[51:48] of the stage 1 translation table base address.
 When z>x register bits[(z1):x] are RES0, and bits[(z1):x] of the translation table base address are zero.
 When x>6 register bits[(x1):6] are RES0.
 Register bit[1] is RES0.
 Bits[5:2] of the stage 1 translation table base address are zero.
 In an implementation that includes ARMv8.2TTCNP bit[0] of the stage 1 translation table base address is zero.
In an implementation that includes ARMv8.2LPA:
 A TCR_EL2.{I}PS value of 0b110, that selects an OA size of 52 bits, is permitted only when using the 64KB translation granule.
 The OA size is specified by:
When the value of ID_AA64MMFR0_EL1.PARange indicates that the implementation does not support a 52 bit PA size, if a translation table lookup uses this register with the 64KB translation granule when the value of TCR_EL2.{I}PS is 0b110 and the value of register bits[5:2] is nonzero, an Address size fault is generated.
If the Effective value of TCR_EL2.{I}PS is not 0b110 then:
 Register bits[47:x] hold bits[47:x] of the stage 1 translation table base address.
 Register bits[(x1):1] are RES0.
 If the implementation supports 52bit PAs and IPAs, then bits[51:48] of the translation table base addresses used in this stage of translation are 0b0000.
This definition applies:
 To an implementation that includes ARMv8.2LPA and is using a translation granule smaller than 64KB.
 To any implementation that does not include ARMv8.2LPA.
If any TTBR0_EL2[47:0] bit that is defined as RES0 has the value 1 when a translation table walk is performed using TTBR0_EL2, then the translation table base address might be misaligned, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:
 Bits[x1:0] of the translation table base address are treated as if all the bits are zero. The value read back from the corresponding register bits is either the value written to the register or zero.
 The result of the calculation of an address for a translation table walk using this register can be corrupted in those bits that are nonzero.
The AArch64 Virtual Memory System Architecture chapter describes how x is calculated based on the value of TCR_EL2.T0SZ, the stage of translation, and the translation granule size.
This field resets to an architecturally UNKNOWN value.
CnP, bit [0]
When ARMv8.2TTCNP is implemented:
When ARMv8.2TTCNP is implemented:
Common not Private. This bit indicates whether each entry that is pointed to by TTBR0_EL2 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR0_EL2.CnP is 1.
CnP  Meaning 

0b0 
The translation table entries pointed to by TTBR0_EL2 for the current translation regime, and ASID if applicable, are permitted to differ from corresponding entries for TTBR0_EL2 for other PEs in the Inner Shareable domain. This is not affected by:

0b1 
The translation table entries pointed to by TTBR0_EL2 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR0_EL2.CnP is 1 and all of the following apply:

This field is permitted to be cached in a TLB.
If the value of the TTBR0_EL2.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR0_EL2s do not point to the same translation table entries when the other conditions specified for the case when the value of CnP is 1 apply, then the results of translations are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values' in the Arm® Architecture Reference Manual, Armv8, for Armv8A architecture profile.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
Accessing the TTBR0_EL2
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic TTBR0_EL2 or TTBR0_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
Accesses to this register use the following encodings:
MRS <Xt>, TTBR0_EL2
op0  op1  CRn  CRm  op2 

0b11  0b100  0b0010  0b0000  0b000 
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then return TTBR0_EL2; elsif PSTATE.EL == EL3 then return TTBR0_EL2;
MSR TTBR0_EL2, <Xt>
op0  op1  CRn  CRm  op2 

0b11  0b100  0b0010  0b0000  0b000 
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then TTBR0_EL2 = X[t]; elsif PSTATE.EL == EL3 then TTBR0_EL2 = X[t];
MRS <Xt>, TTBR0_EL1
op0  op1  CRn  CRm  op2 

0b11  0b000  0b0010  0b0000  0b000 
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x200]; else return TTBR0_EL1; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then return TTBR0_EL2; else return TTBR0_EL1; elsif PSTATE.EL == EL3 then return TTBR0_EL1;
MSR TTBR0_EL1, <Xt>
op0  op1  CRn  CRm  op2 

0b11  0b000  0b0010  0b0000  0b000 
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x200] = X[t]; else TTBR0_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then TTBR0_EL2 = X[t]; else TTBR0_EL1 = X[t]; elsif PSTATE.EL == EL3 then TTBR0_EL1 = X[t];