EDRCR, External Debug Reserve Control Register
The EDRCR characteristics are:
Purpose
This register is used to allow imprecise entry to Debug state and clear sticky bits in EDSCR.
Configuration
EDRCR is in the Core power domain.
Attributes
EDRCR is a 32-bit register.
Field descriptions
The EDRCR bit assignments are:
Bits [31:5]
Reserved, RES0.
CBRRQ, bit [4]
Allow imprecise entry to Debug state. The actions on writing to this bit are:
| CBRRQ | Meaning |
|---|---|
| 0b0 |
No action. |
| 0b1 |
Allow imprecise entry to Debug state, for example by canceling pending bus accesses. |
Setting this bit to 1 allows a debugger to request imprecise entry to Debug state. An External Debug Request debug event must be pending before the debugger sets this bit to 1.
This feature is optional. If this feature is not implemented, writes to this bit are ignored.
CSPA, bit [3]
Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The actions on writing to this bit are:
| CSPA | Meaning |
|---|---|
| 0b0 |
No action. |
| 0b1 |
Clear the EDSCR.PipeAdv bit to 0. |
CSE, bit [2]
Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing to this bit are:
| CSE | Meaning |
|---|---|
| 0b0 |
No action. |
| 0b1 |
Clear the EDSCR.{TXU, RXO, ERR} bits, and, if the PE is in Debug state, the EDSCR.ITO bit, to 0. |
Bits [1:0]
Reserved, RES0.
Accessing the EDRCR
EDRCR can be accessed through the external debug interface:
| Component | Offset | Instance |
|---|---|---|
| Debug | 0x090 | EDRCR |
This interface is accessible as follows:
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and SoftwareLockStatus() accesses to this register are WI.
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and !SoftwareLockStatus() accesses to this register are WO.
- Otherwise accesses to this register generate an error response.