AMEVTYPER0<n>, Activity Monitors Event Type Registers 0, n = 0 - 15
The AMEVTYPER0<n> characteristics are:
Purpose
Provides information on the events that an architected activity monitor event counter AMEVCNTR0<n> counts.
Configuration
AArch32 System register AMEVTYPER0<n> bits [31:0] are architecturally mapped to AArch64 System register AMEVTYPER0<n>_EL0[31:0] .
AArch32 System register AMEVTYPER0<n> bits [31:0] are architecturally mapped to External register AMEVTYPER0<n>[31:0] .
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMEVTYPER0<n> are UNDEFINED.
Attributes
AMEVTYPER0<n> is a 32-bit register.
Field descriptions
The AMEVTYPER0<n> bit assignments are:
Bits [31:16]
Reserved, RES0.
evtCount, bits [15:0]
Event to count. The event number of the event that is counted by the architected activity monitor event counter AMEVCNTR0<n>. The value of this field is architecturally mandated for each architected counter.
The following table shows the mapping between required event numbers and the corresponding counters:
| evtCount | Meaning | Applies when |
|---|---|---|
| 0x0011 |
Processor frequency cycles | When n == 0 |
| 0x4004 |
Constant frequency cycles | When n == 1 |
| 0x0008 |
Instructions retired | When n == 2 |
| 0x4005 |
Memory stall cycles | When n == 3 |
Accessing the AMEVTYPER0<n>
If <n> is greater than or equal to the number of architected activity monitor event counters, reads and writes of AMEVTYPER0<n> are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:
- Accesses to the register are UNDEFINED.
- Accesses to the register behave as RAZ/WI.
- Accesses to the register execute as a NOP.
AMCGCR.CG0NC identifies the number of architected activity monitor event counters.
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1101 | 0b011:n[3] | n[2:0] |
if PSTATE.EL == EL0 then
if !ELUsingAArch32(EL1) && AMUSERENR_EL0.EN == '0' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
else
AArch64.AArch32SystemAccessTrap(EL1, 0x03);
elsif ELUsingAArch32(EL1) && AMUSERENR.EN == '0' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then
AArch32.TakeHypTrapException(0x00);
else
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> != '11' && HSTR_EL2.T13 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCPTR.TAM == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
else
return AMEVTYPER0[UInt(CRm<0>:opc2<2:0>)];
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T13 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCPTR.TAM == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
else
return AMEVTYPER0[UInt(CRm<0>:opc2<2:0>)];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
else
return AMEVTYPER0[UInt(CRm<0>:opc2<2:0>)];
elsif PSTATE.EL == EL3 then
return AMEVTYPER0[UInt(CRm<0>:opc2<2:0>)];