ICV_AP1R<n>, Interrupt Controller Virtual Active Priorities Group 1 Registers, n = 0 - 3
The ICV_AP1R<n> characteristics are:
Purpose
Provides information about virtual Group 1 active priorities.
Configuration
AArch32 System register ICV_AP1R<n> bits [31:0] are architecturally mapped to AArch64 System register ICV_AP1R<n>_EL1[31:0] .
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch32. If the PE resets into EL3 using AArch32 they apply only to the Secure instance of the register. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
Attributes
ICV_AP1R<n> is a 32-bit register.
Field descriptions
The ICV_AP1R<n> bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED, bits [31:0]
IMPLEMENTATION DEFINED.
This field resets to 0.
The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active.
Accessing the ICV_AP1R<n>
Writing to these registers with any value other than the last read value of the register (or 0x00000000 when there are no Group 1 active priorities) might result in UNPREDICTABLE behavior of the virtual interrupt prioritization system, causing:
- Interrupts that should preempt execution to not preempt execution.
- Interrupts that should not preempt execution to preempt execution.
ICV_AP1R1 is only implemented in implementations that support 6 or more bits of priority. ICV_AP1R2 and ICV_AP1R3 are only implemented in implementations that support 7 bits of priority. Unimplemented registers are UNDEFINED.
Writing to the active priority registers in any order other than the following order might result in UNPREDICTABLE behavior of the interrupt prioritization system:
- ICV_AP0R<n>.
- ICV_AP1R<n>.
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b1001 | 0b0:n[1:0] |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif ICC_SRE.SRE == '0' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL1 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TALL1 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then
return ICV_AP1R[UInt(opc2<1:0>)];
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.IMO == '1' then
return ICV_AP1R[UInt(opc2<1:0>)];
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.IRQ == '1' then
AArch32.TakeMonitorTrapException();
elsif HaveEL(EL3) then
if SCR.NS == '0' then
return ICC_AP1R_S[UInt(opc2<1:0>)];
else
return ICC_AP1R_NS[UInt(opc2<1:0>)];
else
return ICC_AP1R[UInt(opc2<1:0>)];
elsif PSTATE.EL == EL2 then
if ICC_HSRE.SRE == '0' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.IRQ == '1' then
AArch32.TakeMonitorTrapException();
elsif HaveEL(EL3) then
return ICC_AP1R_NS[UInt(opc2<1:0>)];
else
return ICC_AP1R[UInt(opc2<1:0>)];
elsif PSTATE.EL == EL3 then
if ICC_MSRE.SRE == '0' then
UNDEFINED;
else
if SCR.NS == '0' then
return ICC_AP1R_S[UInt(opc2<1:0>)];
else
return ICC_AP1R_NS[UInt(opc2<1:0>)];
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b1001 | 0b0:n[1:0] |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif ICC_SRE.SRE == '0' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL1 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TALL1 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then
ICV_AP1R[UInt(opc2<1:0>)] = R[t];
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.IMO == '1' then
ICV_AP1R[UInt(opc2<1:0>)] = R[t];
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.IRQ == '1' then
AArch32.TakeMonitorTrapException();
elsif HaveEL(EL3) then
if SCR.NS == '0' then
ICC_AP1R_S[UInt(opc2<1:0>)] = R[t];
else
ICC_AP1R_NS[UInt(opc2<1:0>)] = R[t];
else
ICC_AP1R[UInt(opc2<1:0>)] = R[t];
elsif PSTATE.EL == EL2 then
if ICC_HSRE.SRE == '0' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.IRQ == '1' then
AArch32.TakeMonitorTrapException();
elsif HaveEL(EL3) then
ICC_AP1R_NS[UInt(opc2<1:0>)] = R[t];
else
ICC_AP1R[UInt(opc2<1:0>)] = R[t];
elsif PSTATE.EL == EL3 then
if ICC_MSRE.SRE == '0' then
UNDEFINED;
else
if SCR.NS == '0' then
ICC_AP1R_S[UInt(opc2<1:0>)] = R[t];
else
ICC_AP1R_NS[UInt(opc2<1:0>)] = R[t];